netdev - Re: [PATCH V5 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node

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Message-ID: <07467780-c84a-442d-b4b8-a96a5c2630eb@quicinc.com>
Date: Fri, 4 Oct 2024 13:30:57 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Devi Priya
	<quic_devipriy@...cinc.com>
CC: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <konrad.dybcio@...aro.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <p.zabel@...gutronix.de>,
        <richardcochran@...il.com>, <geert+renesas@...der.be>,
        <neil.armstrong@...aro.org>, <arnd@...db.de>,
        <m.szyprowski@...sung.com>, <nfraprado@...labora.com>,
        <u-kumar1@...com>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <netdev@...r.kernel.org>
Subject: Re: [PATCH V5 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc
 node



On 6/26/2024 11:43 PM, Dmitry Baryshkov wrote:
> On Wed, Jun 26, 2024 at 08:03:01PM GMT, Devi Priya wrote:
>> Add a node for the nss clock controller found on ipq9574 based devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
>> ---
>>  Changes in V5:
>> 	- Dropped interconnects from nsscc node and added 
>> 	  interconnect-cells to NSS clock provider so that it can be used
>> 	  as icc provider.
>>
>>  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++
>>  1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 48dfafea46a7..b6f8800bf63c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -11,6 +11,8 @@
>>  #include <dt-bindings/interconnect/qcom,ipq9574.h>
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>  #include <dt-bindings/thermal/thermal.h>
>>  
>>  / {
>> @@ -19,6 +21,24 @@ / {
>>  	#size-cells = <2>;
>>  
>>  	clocks {
>> +		bias_pll_cc_clk: bias-pll-cc-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <1200000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <461500000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
> 
> What is the source for these clocks? Is it really an on-board crystal?
> 
Hi Dmitry,

Sorry for the delayed response.

No, the CMN PLL [1] is the source for these clocks. Will remove these
nodes and set these entries to 0 in the nsscc node until the CMN
PLL driver posted with these clocks.

1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com/

Thanks & Regards,
Manikanta.