netdev - [PATCH v6 6/7] arm64: dts: qcom: ipq9574: Add nsscc node

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Message-ID: <20241004080332.853503-7-quic_mmanikan@quicinc.com>
Date: Fri, 4 Oct 2024 13:33:31 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <konradybcio@...nel.org>, <catalin.marinas@....com>, <will@...nel.org>,
        <p.zabel@...gutronix.de>, <richardcochran@...il.com>,
        <geert+renesas@...der.be>, <dmitry.baryshkov@...aro.org>,
        <neil.armstrong@...aro.org>, <arnd@...db.de>,
        <nfraprado@...labora.com>, <quic_anusha@...cinc.com>,
        <quic_mmanikan@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <netdev@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: [PATCH v6 6/7] arm64: dts: qcom: ipq9574: Add nsscc node

From: Devi Priya <quic_devipriy@...cinc.com>

Add a node for the nss clock controller found on ipq9574 based devices.

Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
---
Changes in V6:
	- Remove bias_pll_cc_clk, bias_pll_nss_noc_clk, bias_pll_ubi_nc_clk nodes from DTS.
	  Because these clocks will be enabled by CMN PLL [1]. Until the CMN PLL driver posted
	  with these clocks set these entries to 0 in the nsscc node.
	  1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com/
	- Fixed the title

 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 08a82a5cf667..943c5757c36e 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -11,6 +11,8 @@
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -756,6 +758,27 @@ frame@...8000 {
 				status = "disabled";
 			};
 		};
+
+		nsscc: clock-controller@...00000 {
+			compatible = "qcom,ipq9574-nsscc";
+			reg = <0x39b00000 0x80000>;
+			clocks = <&xo_board_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&gcc GPLL0_OUT_AUX>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&gcc GCC_NSSCC_CLK>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			#interconnect-cells = <1>;
+		};
 	};
 
 	thermal-zones {
-- 
2.34.1