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Message-Id: <E1t1P3X-000EJx-ES@rmk-PC.armlinux.org.uk>
Date: Thu, 17 Oct 2024 12:52:39 +0100
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>
Cc: "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Jose Abreu <Jose.Abreu@...opsys.com>,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>
Subject: [PATCH net-next 1/7] net: pcs: xpcs: use generic register definitions
As a general policy, we refer our generic register definitions over
vendor specific definitions. In XPCS, it appears that the register
layout follows a BMCR, BMSR and ADVERTISE register definition. We
already refer to this BMCR register using several different macros
which is confusing.
Convert the following register definitions to generic versions:
DW_VR_MII_MMD_CTRL => MII_BMCR
MDIO_CTRL1 => MII_BMCR
AN_CL37_EN => BMCR_ANENABLE
SGMII_SPEED_SS6 => BMCR_SPEED1000
SGMII_SPEED_SS13 => BMCR_SPEED100
MDIO_CTRL1_RESET => BMCR_RESET
DW_VR_MII_MMD_STS => MII_BMSR
DW_VR_MII_MMD_STS_LINK_STS => BMSR_LSTATUS
DW_FULL_DUPLEX => ADVERTISE_1000XFULL
iDW_HALF_DUPLEX => ADVERTISE_1000XHALF
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
drivers/net/pcs/pcs-xpcs.c | 64 ++++++++++++++++++++------------------
drivers/net/pcs/pcs-xpcs.h | 12 -------
2 files changed, 34 insertions(+), 42 deletions(-)
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index c69421e80d19..a5e2d93db285 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -223,8 +223,8 @@ static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
int ret, val;
ret = read_poll_timeout(xpcs_read, val,
- val < 0 || !(val & MDIO_CTRL1_RESET),
- 50000, 600000, true, xpcs, dev, MDIO_CTRL1);
+ val < 0 || !(val & BMCR_RESET),
+ 50000, 600000, true, xpcs, dev, MII_BMCR);
if (val < 0)
ret = val;
@@ -250,7 +250,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
return -EINVAL;
}
- ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
+ ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET);
if (ret < 0)
return ret;
@@ -343,7 +343,7 @@ static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
if (ret < 0)
goto out;
- ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, DW_USXGMII_SS_MASK,
+ ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK,
speed_sel | DW_USXGMII_FULL);
if (ret < 0)
goto out;
@@ -646,19 +646,21 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
* speed/duplex mode change by HW after SGMII AN complete)
* 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
*
+ * Note that VR_MII_MMD_CTRL is MII_BMCR.
+ *
* Note: Since it is MAC side SGMII, there is no need to set
* SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
* PHY about the link state change after C28 AN is completed
* between PHY and Link Partner. There is also no need to
* trigger AN restart for MAC-side SGMII.
*/
- mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+ mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
if (mdio_ctrl < 0)
return mdio_ctrl;
- if (mdio_ctrl & AN_CL37_EN) {
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
- mdio_ctrl & ~AN_CL37_EN);
+ if (mdio_ctrl & BMCR_ANENABLE) {
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ mdio_ctrl & ~BMCR_ANENABLE);
if (ret < 0)
return ret;
}
@@ -696,8 +698,8 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
return ret;
if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
- mdio_ctrl | AN_CL37_EN);
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ mdio_ctrl | BMCR_ANENABLE);
return ret;
}
@@ -715,14 +717,16 @@ static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
* be disabled first:-
* 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
* 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
+ *
+ * Note that VR_MII_MMD_CTRL is MII_BMCR.
*/
- mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+ mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
if (mdio_ctrl < 0)
return mdio_ctrl;
- if (mdio_ctrl & AN_CL37_EN) {
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
- mdio_ctrl & ~AN_CL37_EN);
+ if (mdio_ctrl & BMCR_ANENABLE) {
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ mdio_ctrl & ~BMCR_ANENABLE);
if (ret < 0)
return ret;
}
@@ -760,8 +764,8 @@ static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
return ret;
if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
- mdio_ctrl | AN_CL37_EN);
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ mdio_ctrl | BMCR_ANENABLE);
if (ret < 0)
return ret;
}
@@ -780,9 +784,9 @@ static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
if (ret < 0)
return ret;
- return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
- AN_CL37_EN | SGMII_SPEED_SS6 | SGMII_SPEED_SS13,
- SGMII_SPEED_SS6);
+ return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100,
+ BMCR_SPEED1000);
}
static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
@@ -972,14 +976,14 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
state->link = true;
- speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
+ speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
if (speed < 0)
return speed;
- speed &= SGMII_SPEED_SS13 | SGMII_SPEED_SS6;
- if (speed == SGMII_SPEED_SS6)
+ speed &= BMCR_SPEED100 | BMCR_SPEED1000;
+ if (speed == BMCR_SPEED1000)
state->speed = SPEED_1000;
- else if (speed == SGMII_SPEED_SS13)
+ else if (speed == BMCR_SPEED100)
state->speed = SPEED_100;
else if (speed == 0)
state->speed = SPEED_10;
@@ -988,9 +992,9 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
if (duplex < 0)
return duplex;
- if (duplex & DW_FULL_DUPLEX)
+ if (duplex & ADVERTISE_1000XFULL)
state->duplex = DUPLEX_FULL;
- else if (duplex & DW_HALF_DUPLEX)
+ else if (duplex & ADVERTISE_1000XHALF)
state->duplex = DUPLEX_HALF;
xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
@@ -1039,13 +1043,13 @@ static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
{
int ret;
- ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS);
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
if (ret < 0) {
state->link = 0;
return ret;
}
- state->link = !!(ret & DW_VR_MII_MMD_STS_LINK_STS);
+ state->link = !!(ret & BMSR_LSTATUS);
if (!state->link)
return 0;
@@ -1109,7 +1113,7 @@ static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode,
return;
val = mii_bmcr_encode_fixed(speed, duplex);
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, val);
if (ret)
dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n",
__func__, ERR_PTR(ret));
@@ -1141,7 +1145,7 @@ static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode,
dev_err(&xpcs->mdiodev->dev, "%s: half duplex not supported\n",
__func__);
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, val);
if (ret)
dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n",
__func__, ERR_PTR(ret));
@@ -1164,7 +1168,7 @@ static void xpcs_an_restart(struct phylink_pcs *pcs)
{
struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
- xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, BMCR_ANRESTART,
+ xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART,
BMCR_ANRESTART);
}
diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h
index 9a22eed4404d..adc5a0b3c883 100644
--- a/drivers/net/pcs/pcs-xpcs.h
+++ b/drivers/net/pcs/pcs-xpcs.h
@@ -54,9 +54,6 @@
/* Clause 37 Defines */
/* VR MII MMD registers offsets */
-#define DW_VR_MII_MMD_CTRL 0x0000
-#define DW_VR_MII_MMD_STS 0x0001
-#define DW_VR_MII_MMD_STS_LINK_STS BIT(2)
#define DW_VR_MII_DIG_CTRL1 0x8000
#define DW_VR_MII_AN_CTRL 0x8001
#define DW_VR_MII_AN_INTR_STS 0x8002
@@ -93,15 +90,6 @@
#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
-/* SR MII MMD Control defines */
-#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
-#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
-#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
-
-/* SR MII MMD AN Advertisement defines */
-#define DW_HALF_DUPLEX BIT(6)
-#define DW_FULL_DUPLEX BIT(5)
-
/* VR MII EEE Control 0 defines */
#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
--
2.30.2
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