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Message-ID: <887362d6-d86d-ce2d-f4b6-e352b84c4d91@amd.com>
Date: Fri, 18 Oct 2024 10:35:04 +0100
From: Alejandro Lucero Palau <alucerop@....com>
To: Ben Cheatham <benjamin.cheatham@....com>, alejandro.lucero-palau@....com
Cc: linux-cxl@...r.kernel.org, netdev@...r.kernel.org,
dan.j.williams@...el.com, martin.habets@...inx.com, edward.cree@....com,
davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com, edumazet@...gle.com
Subject: Re: [PATCH v4 05/26] cxl: move pci generic code
On 10/17/24 22:49, Ben Cheatham wrote:
> On 10/17/24 11:52 AM, alejandro.lucero-palau@....com wrote:
>> From: Alejandro Lucero <alucerop@....com>
>>
>> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization
>> meanwhile cxl/pci.c implements the functionality for a Type3 device
>> initialization.
>>
>> Move helper functions from cxl/pci.c to cxl/pci/pci.c in order to be
> Wrong path, cxl/pci/pci.c should be cxl/core/pci.c.
Oh, good catch.
I'll fix it.
Thanks
>> exported and shared with CXL Type2 device initialization.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> ---
>> drivers/cxl/core/pci.c | 62 ++++++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxlpci.h | 3 ++
>> drivers/cxl/pci.c | 61 -----------------------------------------
>> 3 files changed, 65 insertions(+), 61 deletions(-)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index fa2a5e216dc3..99acc258722d 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -1079,6 +1079,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port)
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL);
>>
>> +/*
>> + * Assume that any RCIEP that emits the CXL memory expander class code
>> + * is an RCD
>> + */
>> +bool is_cxl_restricted(struct pci_dev *pdev)
>> +{
>> + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL);
>> +
>> +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
>> + struct cxl_register_map *map)
>> +{
>> + struct cxl_port *port;
>> + struct cxl_dport *dport;
>> + resource_size_t component_reg_phys;
>> +
>> + *map = (struct cxl_register_map) {
>> + .host = &pdev->dev,
>> + .resource = CXL_RESOURCE_NONE,
>> + };
>> +
>> + port = cxl_pci_find_port(pdev, &dport);
>> + if (!port)
>> + return -EPROBE_DEFER;
>> +
>> + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
>> +
>> + put_device(&port->dev);
>> +
>> + if (component_reg_phys == CXL_RESOURCE_NONE)
>> + return -ENXIO;
>> +
>> + map->resource = component_reg_phys;
>> + map->reg_type = CXL_REGLOC_RBI_COMPONENT;
>> + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
>> +
>> + return 0;
>> +}
>> +
>> +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>> + struct cxl_register_map *map, unsigned long *caps)
>> +{
>> + int rc;
>> +
>> + rc = cxl_find_regblock(pdev, type, map);
>> +
>> + /*
>> + * If the Register Locator DVSEC does not exist, check if it
>> + * is an RCH and try to extract the Component Registers from
>> + * an RCRB.
>> + */
>> + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
>> + rc = cxl_rcrb_get_comp_regs(pdev, map);
>> +
>> + if (rc)
>> + return rc;
>> +
>> + return cxl_setup_regs(map, caps);
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL);
>> +
>> bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps,
>> unsigned long *current_caps)
>> {
>> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
>> index eb59019fe5f3..985cca3c3350 100644
>> --- a/drivers/cxl/cxlpci.h
>> +++ b/drivers/cxl/cxlpci.h
>> @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port);
>> void cxl_cor_error_detected(struct pci_dev *pdev);
>> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>> pci_channel_state_t state);
>> +bool is_cxl_restricted(struct pci_dev *pdev);
>> +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>> + struct cxl_register_map *map, unsigned long *caps);
>> #endif /* __CXL_PCI_H__ */
>> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
>> index 89c8ac1a61fd..e9333211e18f 100644
>> --- a/drivers/cxl/pci.c
>> +++ b/drivers/cxl/pci.c
>> @@ -463,67 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail)
>> return 0;
>> }
>>
>> -/*
>> - * Assume that any RCIEP that emits the CXL memory expander class code
>> - * is an RCD
>> - */
>> -static bool is_cxl_restricted(struct pci_dev *pdev)
>> -{
>> - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
>> -}
>> -
>> -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
>> - struct cxl_register_map *map)
>> -{
>> - struct cxl_port *port;
>> - struct cxl_dport *dport;
>> - resource_size_t component_reg_phys;
>> -
>> - *map = (struct cxl_register_map) {
>> - .host = &pdev->dev,
>> - .resource = CXL_RESOURCE_NONE,
>> - };
>> -
>> - port = cxl_pci_find_port(pdev, &dport);
>> - if (!port)
>> - return -EPROBE_DEFER;
>> -
>> - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
>> -
>> - put_device(&port->dev);
>> -
>> - if (component_reg_phys == CXL_RESOURCE_NONE)
>> - return -ENXIO;
>> -
>> - map->resource = component_reg_phys;
>> - map->reg_type = CXL_REGLOC_RBI_COMPONENT;
>> - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
>> -
>> - return 0;
>> -}
>> -
>> -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>> - struct cxl_register_map *map,
>> - unsigned long *caps)
>> -{
>> - int rc;
>> -
>> - rc = cxl_find_regblock(pdev, type, map);
>> -
>> - /*
>> - * If the Register Locator DVSEC does not exist, check if it
>> - * is an RCH and try to extract the Component Registers from
>> - * an RCRB.
>> - */
>> - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
>> - rc = cxl_rcrb_get_comp_regs(pdev, map);
>> -
>> - if (rc)
>> - return rc;
>> -
>> - return cxl_setup_regs(map, caps);
>> -}
>> -
>> static int cxl_pci_ras_unmask(struct pci_dev *pdev)
>> {
>> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
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