netdev - [PATCH net-next v2 03/15] net: sparx5: change frequency calculation for SDLB's

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Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com>
Date: Thu, 24 Oct 2024 00:01:22 +0200
From: Daniel Machon <daniel.machon@...rochip.com>
To: "David S. Miller" <davem@...emloft.net>, Eric Dumazet
	<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
	<pabeni@...hat.com>, Andrew Lunn <andrew+netdev@...n.ch>, Lars Povlsen
	<lars.povlsen@...rochip.com>, Steen Hegelund <Steen.Hegelund@...rochip.com>,
	<horatiu.vultur@...rochip.com>, <jensemil.schulzostergaard@...rochip.com>,
	<Parthiban.Veerasooran@...rochip.com>, <Raju.Lakkaraju@...rochip.com>,
	<UNGLinuxDriver@...rochip.com>, Richard Cochran <richardcochran@...il.com>,
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, <jacob.e.keller@...el.com>,
	<ast@...erby.net>, <maxime.chevallier@...tlin.com>, <horms@...nel.org>
CC: <netdev@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, Steen Hegelund
	<steen.hegelund@...rochip.com>, <devicetree@...r.kernel.org>
Subject: [PATCH net-next v2 03/15] net: sparx5: change frequency
 calculation for SDLB's

In preparation for lan969x, rework the function that calculates the SDLB
(Service Dual Leacky Bucket) clock. This is required, as the
HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock
from the core clock, using the sparx5_clk_period() function. The clock
stays the same before and after this patch, only now,
sparx5_sdlb_clk_hz_get() can be used for lan969x too.

Reviewed-by: Steen Hegelund <Steen.Hegelund@...rochip.com>
Signed-off-by: Daniel Machon <daniel.machon@...rochip.com>
---
 drivers/net/ethernet/microchip/sparx5/sparx5_main.h |  2 +-
 drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 10 +++-------
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
index f117cf65cf8c..2a3b4e855590 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
@@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx);
 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval,
 			      u64 rate);
 
-int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
+u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst);
 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group);
 
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c
index df1d15600aad..98a3f44c569c 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c
@@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx)
 	return &sdlb_groups[idx];
 }
 
-int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5)
+u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5)
 {
-	u32 clk_per_100ps;
 	u64 clk_hz;
 
-	clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5,
-							   HSCH_SYS_CLK_PER));
-	if (!clk_per_100ps)
-		clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT;
+	clk_hz = (10 * 1000 * 1000) /
+		 (sparx5_clk_period(sparx5->coreclock) / 100);
 
-	clk_hz = (10 * 1000 * 1000) / clk_per_100ps;
 	return clk_hz *= 1000;
 }
 

-- 
2.34.1