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Message-ID: <20241024084806.GG402847@kernel.org>
Date: Thu, 24 Oct 2024 09:48:06 +0100
From: Simon Horman <horms@...nel.org>
To: Jacob Keller <jacob.e.keller@...el.com>
Cc: Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Jeff Garzik <jgarzik@...hat.com>,
Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>,
Piotr Raczynski <piotr.raczynski@...el.com>,
Vadim Fedorenko <vadim.fedorenko@...ux.dev>,
Milena Olech <milena.olech@...el.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
Michal Michalik <michal.michalik@...el.com>,
netdev <netdev@...r.kernel.org>, Jiri Pirko <jiri@...nulli.us>,
Karol Kolacinski <karol.kolacinski@...el.com>,
Pucha Himasekhar Reddy <himasekharx.reddy.pucha@...el.com>
Subject: Re: [PATCH net 3/3] ice: fix crash on probe for DPLL enabled E810 LOM
On Mon, Oct 21, 2024 at 04:26:26PM -0700, Jacob Keller wrote:
> From: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
>
> The E810 Lan On Motherboard (LOM) design is vendor specific. Intel
> provides the reference design, but it is up to vendor on the final
> product design. For some cases, like Linux DPLL support, the static
> values defined in the driver does not reflect the actual LOM design.
> Current implementation of dpll pins is causing the crash on probe
> of the ice driver for such DPLL enabled E810 LOM designs:
>
> WARNING: (...) at drivers/dpll/dpll_core.c:495 dpll_pin_get+0x2c4/0x330
> ...
> Call Trace:
> <TASK>
> ? __warn+0x83/0x130
> ? dpll_pin_get+0x2c4/0x330
> ? report_bug+0x1b7/0x1d0
> ? handle_bug+0x42/0x70
> ? exc_invalid_op+0x18/0x70
> ? asm_exc_invalid_op+0x1a/0x20
> ? dpll_pin_get+0x117/0x330
> ? dpll_pin_get+0x2c4/0x330
> ? dpll_pin_get+0x117/0x330
> ice_dpll_get_pins.isra.0+0x52/0xe0 [ice]
> ...
>
> The number of dpll pins enabled by LOM vendor is greater than expected
> and defined in the driver for Intel designed NICs, which causes the crash.
>
> Prevent the crash and allow generic pin initialization within Linux DPLL
> subsystem for DPLL enabled E810 LOM designs.
>
> Newly designed solution for described issue will be based on "per HW
> design" pin initialization. It requires pin information dynamically
> acquired from the firmware and is already in progress, planned for
> next-tree only.
>
> Fixes: d7999f5ea64b ("ice: implement dpll interface to control cgu")
> Reviewed-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@...el.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
Reviewed-by: Simon Horman <horms@...nel.org>
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