netdev - [PATCH v8 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out

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Message-ID: <20241025035520.1841792-4-quic_mmanikan@quicinc.com>
Date: Fri, 25 Oct 2024 09:25:16 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <konradybcio@...nel.org>, <catalin.marinas@....com>, <will@...nel.org>,
        <p.zabel@...gutronix.de>, <richardcochran@...il.com>,
        <geert+renesas@...der.be>, <dmitry.baryshkov@...aro.org>,
        <angelogioacchino.delregno@...labora.com>, <neil.armstrong@...aro.org>,
        <arnd@...db.de>, <nfraprado@...labora.com>, <quic_anusha@...cinc.com>,
        <quic_mmanikan@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <netdev@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: [PATCH v8 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock

From: Devi Priya <quic_devipriy@...cinc.com>

Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
---
Changes in V8:
	- No change

 drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0405a2473842..08921bff46da 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 	},
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "gpll0_out_aux",
+		.parent_hws = (const struct clk_hw *[]) {
+			&gpll0_main.clkr.hw
+		},
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+	},
+};
+
 static struct clk_alpha_pll gpll4_main = {
 	.offset = 0x22000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
@@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
 	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
 	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
 	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
+	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
-- 
2.34.1