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Message-ID: <20241025035520.1841792-7-quic_mmanikan@quicinc.com>
Date: Fri, 25 Oct 2024 09:25:19 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
<robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<konradybcio@...nel.org>, <catalin.marinas@....com>, <will@...nel.org>,
<p.zabel@...gutronix.de>, <richardcochran@...il.com>,
<geert+renesas@...der.be>, <dmitry.baryshkov@...aro.org>,
<angelogioacchino.delregno@...labora.com>, <neil.armstrong@...aro.org>,
<arnd@...db.de>, <nfraprado@...labora.com>, <quic_anusha@...cinc.com>,
<quic_mmanikan@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<netdev@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: [PATCH v8 6/7] arm64: dts: qcom: ipq9574: Add nsscc node
From: Devi Priya <quic_devipriy@...cinc.com>
Add a node for the nss clock controller found on ipq9574 based devices.
Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
---
Changes in V8:
- Add cmn_pll NSS_1200MHZ_CLK and PPE_353MHZ_CLK
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 93f66bb83c5a..34f3510ea7ec 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -12,6 +12,8 @@
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -774,6 +776,26 @@ frame@...8000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@...00000 {
+ compatible = "qcom,ipq9574-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&cmn_pll NSS_1200MHZ_CLK>,
+ <&cmn_pll PPE_353MHZ_CLK>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&gcc GCC_NSSCC_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ #interconnect-cells = <1>;
+ };
};
thermal-zones {
--
2.34.1
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