netdev - RE: [PATCH v5 net-next 11/13] net: enetc: optimize the allocation of tx

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Message-ID:
 <PAXPR04MB85108D88299951702116B92388482@PAXPR04MB8510.eurprd04.prod.outlook.com>
Date: Sat, 26 Oct 2024 02:37:11 +0000
From: Wei Fang <wei.fang@....com>
To: Vladimir Oltean <vladimir.oltean@....com>
CC: "davem@...emloft.net" <davem@...emloft.net>, "edumazet@...gle.com"
	<edumazet@...gle.com>, "kuba@...nel.org" <kuba@...nel.org>,
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	"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, Claudiu Manoil <claudiu.manoil@....com>, Clark Wang
	<xiaoning.wang@....com>, Frank Li <frank.li@....com>,
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	<linux-pci@...r.kernel.org>, "alexander.stein@...tq-group.com"
	<alexander.stein@...tq-group.com>
Subject: RE: [PATCH v5 net-next 11/13] net: enetc: optimize the allocation of
 tx_bdr

> On Thu, Oct 24, 2024 at 02:53:26PM +0800, Wei Fang wrote:
> > From: Clark Wang <xiaoning.wang@....com>
> >
> > There is a situation where num_tx_rings cannot be divided by bdr_int_num.
> > For example, num_tx_rings is 8 and bdr_int_num is 3. According to the
> > previous logic, this results in two tx_bdr corresponding memories not
> > being allocated, so when sending packets to tx ring 6 or 7, wild pointers
> > will be accessed. Of course, this issue doesn't exist on LS1028A, because
> > its num_tx_rings is 8, and bdr_int_num is either 1 or 2. However, there
> > is a risk for the upcoming i.MX95. Therefore, it is necessary to ensure
> > that each tx_bdr can be allocated to the corresponding memory.
> >
> > Signed-off-by: Clark Wang <xiaoning.wang@....com>
> > Signed-off-by: Wei Fang <wei.fang@....com>
> > Reviewed-by: Claudiu Manoil <claudiu.manoil@....com>
> > Reviewed-by: Frank Li <Frank.Li@....com>
> > ---
> > v5: no changes
> > ---
> >  drivers/net/ethernet/freescale/enetc/enetc.c | 7 +++++--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c
> b/drivers/net/ethernet/freescale/enetc/enetc.c
> > index bd725561b8a2..bccbeb1f355c 100644
> > --- a/drivers/net/ethernet/freescale/enetc/enetc.c
> > +++ b/drivers/net/ethernet/freescale/enetc/enetc.c
> > @@ -3049,10 +3049,10 @@ static void enetc_int_vector_destroy(struct
> enetc_ndev_priv *priv, int i)
> >  int enetc_alloc_msix(struct enetc_ndev_priv *priv)
> >  {
> >  	struct pci_dev *pdev = priv->si->pdev;
> > +	int v_tx_rings, v_remainder;
> >  	int num_stack_tx_queues;
> >  	int first_xdp_tx_ring;
> >  	int i, n, err, nvec;
> > -	int v_tx_rings;
> >
> >  	nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
> >  	/* allocate MSIX for both messaging and Rx/Tx interrupts */
> > @@ -3066,9 +3066,12 @@ int enetc_alloc_msix(struct enetc_ndev_priv
> *priv)
> >
> >  	/* # of tx rings per int vector */
> >  	v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
> > +	v_remainder = priv->num_tx_rings % priv->bdr_int_num;
> >
> >  	for (i = 0; i < priv->bdr_int_num; i++) {
> > -		err = enetc_int_vector_init(priv, i, v_tx_rings);
> > +		int num_tx_rings = i < v_remainder ? v_tx_rings + 1 : v_tx_rings;
> 
> It took me a moment to understand the mechanism through which this
> works, even though I read the intention in the commit message.
> 
> Do you think this additional comment would help?

Yeah, it does help users understand quickly. I will add this comment.
> 
> 		/* Distribute the remaining TX rings to the first
> 		 * v_tx_rings interrupt vectors
> 		 */
> 
> > +
> > +		err = enetc_int_vector_init(priv, i, num_tx_rings);
> >  		if (err)
> >  			goto fail;
> >  	}
> > --
> > 2.34.1
> >