netdev - Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx

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Message-ID: <wgggariprpp2wczsljy3vw6kp7vhnrifg6soxdgiio2seyctym@4owbzlg3ngum>
Date: Tue, 29 Oct 2024 06:43:03 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Andrew Lunn <andrew@...n.ch>, Inochi Amaoto <inochiama@...il.com>
Cc: Chen Wang <unicorn_wang@...look.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Inochi Amaoto <inochiama@...look.com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Richard Cochran <richardcochran@...il.com>, Jisheng Zhang <jszhang@...nel.org>, 
	Thomas Bonnefille <thomas.bonnefille@...tlin.com>, Liu Gui <kenneth.liu@...hgo.com>, Yixun Lan <dlan@...too.org>, 
	Longbin Li <looong.bin@...il.com>, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx

On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote:
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > @@ -210,6 +210,55 @@ i2c4: i2c@...0000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		gmac0: ethernet@...0000 {
> > +			compatible = "snps,dwmac-3.70a";
> > +			reg = <0x04070000 0x10000>;
> > +			clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
> > +			clock-names = "stmmaceth", "ptp_ref";
> > +			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "macirq";
> > +			phy-handle = <&phy0>;
> > +			phy-mode = "rmii";
> > +			rx-fifo-depth = <8192>;
> > +			tx-fifo-depth = <8192>;
> > +			snps,multicast-filter-bins = <0>;
> > +			snps,perfect-filter-entries = <1>;
> > +			snps,aal;
> > +			snps,txpbl = <8>;
> > +			snps,rxpbl = <8>;
> > +			snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
> > +			snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
> > +			snps,axi-config = <&gmac0_stmmac_axi_setup>;
> > +			status = "disabled";
> > +
> > +			mdio {
> > +				compatible = "snps,dwmac-mdio";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				phy0: phy@0 {
> > +					compatible = "ethernet-phy-ieee802.3-c22";
> > +					reg = <0>;
> > +				};
> > +			};
> 
> It is not clear to me what cv18xx.dtsi represents, 

This is a include file to define common ip for the whole
cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000).

> and where the PHY node should be, here, or in a .dts file. 
> Is this a SOM, and the PHY is on the SOM? 

The phy is on the SoC, it is embedded, and no external phy
is supported. So I think the phy node should stay here, not 
in the dts file.

Regards,
Inochi