netdev - Re: [PATCH net-next v4 1/2] bnxt_en: cache only 24 bits of hw counter

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Message-ID: <CACKFLi=q82S9Ks8raZU3_qhS1+Kac-AT1trceiXL4KMJ_tg=dA@mail.gmail.com>
Date: Wed, 30 Oct 2024 09:53:55 -0700
From: Michael Chan <michael.chan@...adcom.com>
To: Vadim Fedorenko <vadfed@...a.com>
Cc: Vadim Fedorenko <vadim.fedorenko@...ux.dev>, Pavan Chebbi <pavan.chebbi@...adcom.com>, 
	Jakub Kicinski <kuba@...nel.org>, Andrew Lunn <andrew+netdev@...n.ch>, Paolo Abeni <pabeni@...hat.com>, 
	"David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org, 
	Richard Cochran <richardcochran@...il.com>
Subject: Re: [PATCH net-next v4 1/2] bnxt_en: cache only 24 bits of hw counter

On Tue, Oct 29, 2024 at 1:55 PM Vadim Fedorenko <vadfed@...a.com> wrote:
>
> This hardware can provide only 48 bits of cycle counter. We can leave
> only 24 bits in the cache to extend RX timestamps from 32 bits to 48
> bits. Lower 8 bits of the cached value will be used to check for
> roll-over while extending to full 48 bits.
> This change makes cache writes atomic even on 32 bit platforms and we
> can simply use READ_ONCE()/WRITE_ONCE() pair and remove spinlock. The
> configuration structure will be also reduced by 4 bytes.
>
> Signed-off-by: Vadim Fedorenko <vadfed@...a.com>

Thanks.
Reviewed-by: Michael Chan <michael.chan@...adcom.com>

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