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Message-Id: <26b4654455eace4e6d2db951b6f2d752dda0c4c2.1730376866.git.0x1207@gmail.com>
Date: Thu, 31 Oct 2024 20:37:56 +0800
From: Furong Xu <0x1207@...il.com>
To: netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Vladimir Oltean <olteanv@...il.com>,
Andrew Lunn <andrew@...n.ch>,
Simon Horman <horms@...nel.org>,
andrew+netdev@...n.ch,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
xfr@...look.com,
Furong Xu <0x1207@...il.com>
Subject: [PATCH net-next v7 2/8] net: stmmac: Rework macro definitions for gmac4 and xgmac
Rename and add macro definitions to better reuse them in common code.
Signed-off-by: Furong Xu <0x1207@...il.com>
Reviewed-by: Simon Horman <horms@...nel.org>
---
.../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 77 ++++++++++---------
1 file changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
index 59e666668ac1..4d5a1704ed61 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
@@ -9,23 +9,23 @@
#include "dwmac5.h"
#include "dwxgmac2.h"
-#define MAC_FPE_CTRL_STS 0x00000234
-#define TRSP BIT(19)
-#define TVER BIT(18)
-#define RRSP BIT(17)
-#define RVER BIT(16)
-#define SRSP BIT(2)
-#define SVER BIT(1)
-#define EFPE BIT(0)
-
-#define MTL_FPE_CTRL_STS 0x00000c90
+#define GMAC5_MAC_FPE_CTRL_STS 0x00000234
+#define XGMAC_MAC_FPE_CTRL_STS 0x00000280
+
+#define GMAC5_MTL_FPE_CTRL_STS 0x00000c90
+#define XGMAC_MTL_FPE_CTRL_STS 0x00001090
/* Preemption Classification */
-#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8)
+#define FPE_MTL_PREEMPTION_CLASS GENMASK(15, 8)
/* Additional Fragment Size of preempted frames */
-#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0)
+#define FPE_MTL_ADD_FRAG_SZ GENMASK(1, 0)
-#define XGMAC_FPE_CTRL_STS 0x00000280
-#define XGMAC_EFPE BIT(0)
+#define STMMAC_MAC_FPE_CTRL_STS_TRSP BIT(19)
+#define STMMAC_MAC_FPE_CTRL_STS_TVER BIT(18)
+#define STMMAC_MAC_FPE_CTRL_STS_RRSP BIT(17)
+#define STMMAC_MAC_FPE_CTRL_STS_RVER BIT(16)
+#define STMMAC_MAC_FPE_CTRL_STS_SRSP BIT(2)
+#define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1)
+#define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0)
void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
{
@@ -62,11 +62,11 @@ void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 value = cfg->fpe_csr;
if (type == MPACKET_VERIFY)
- value |= SVER;
+ value |= STMMAC_MAC_FPE_CTRL_STS_SVER;
else if (type == MPACKET_RESPONSE)
- value |= SRSP;
+ value |= STMMAC_MAC_FPE_CTRL_STS_SRSP;
- writel(value, ioaddr + MAC_FPE_CTRL_STS);
+ writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS);
}
void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
@@ -198,7 +198,7 @@ void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 value;
if (tx_enable) {
- cfg->fpe_csr = EFPE;
+ cfg->fpe_csr = STMMAC_MAC_FPE_CTRL_STS_EFPE;
value = readl(ioaddr + GMAC_RXQ_CTRL1);
value &= ~GMAC_RXQCTRL_FPRQ;
value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
@@ -206,14 +206,14 @@ void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
} else {
cfg->fpe_csr = 0;
}
- writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS);
+ writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS);
value = readl(ioaddr + GMAC_INT_EN);
if (pmac_enable) {
if (!(value & GMAC_INT_FPE_EN)) {
/* Dummy read to clear any pending masked interrupts */
- readl(ioaddr + MAC_FPE_CTRL_STS);
+ readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS);
value |= GMAC_INT_FPE_EN;
}
@@ -234,24 +234,24 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
/* Reads from the MAC_FPE_CTRL_STS register should only be performed
* here, since the status flags of MAC_FPE_CTRL_STS are "clear on read"
*/
- value = readl(ioaddr + MAC_FPE_CTRL_STS);
+ value = readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS);
- if (value & TRSP) {
+ if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) {
status |= FPE_EVENT_TRSP;
netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n");
}
- if (value & TVER) {
+ if (value & STMMAC_MAC_FPE_CTRL_STS_TVER) {
status |= FPE_EVENT_TVER;
netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n");
}
- if (value & RRSP) {
+ if (value & STMMAC_MAC_FPE_CTRL_STS_RRSP) {
status |= FPE_EVENT_RRSP;
netdev_dbg(dev, "FPE: Respond mPacket is received\n");
}
- if (value & RVER) {
+ if (value & STMMAC_MAC_FPE_CTRL_STS_RVER) {
status |= FPE_EVENT_RVER;
netdev_dbg(dev, "FPE: Verify mPacket is received\n");
}
@@ -261,16 +261,17 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr)
{
- return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS));
+ return FIELD_GET(FPE_MTL_ADD_FRAG_SZ,
+ readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS));
}
void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size)
{
u32 value;
- value = readl(ioaddr + MTL_FPE_CTRL_STS);
- writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ),
- ioaddr + MTL_FPE_CTRL_STS);
+ value = readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS);
+ writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ),
+ ioaddr + GMAC5_MTL_FPE_CTRL_STS);
}
#define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mapping"
@@ -321,9 +322,9 @@ int dwmac5_fpe_map_preemption_class(struct net_device *ndev,
}
update_mapping:
- val = readl(priv->ioaddr + MTL_FPE_CTRL_STS);
- writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS),
- priv->ioaddr + MTL_FPE_CTRL_STS);
+ val = readl(priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS);
+ writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS),
+ priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS);
return 0;
}
@@ -335,11 +336,11 @@ void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 value;
if (!tx_enable) {
- value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
+ value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS);
- value &= ~XGMAC_EFPE;
+ value &= ~STMMAC_MAC_FPE_CTRL_STS_EFPE;
- writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
+ writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS);
return;
}
@@ -348,7 +349,7 @@ void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
value |= (num_rxq - 1) << XGMAC_RQ_SHIFT;
writel(value, ioaddr + XGMAC_RXQ_CTRL1);
- value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
- value |= XGMAC_EFPE;
- writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
+ value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS);
+ value |= STMMAC_MAC_FPE_CTRL_STS_EFPE;
+ writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS);
}
--
2.34.1
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