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Message-ID: <799753305484d74cb9d194347743ff986da071d5.camel@castellotti.net>
Date: Fri, 15 Nov 2024 00:57:10 +0100
From: Erny <ernesto@...tellotti.net>
To: Tore Amundsen <tore@...ndsen.org>
Cc: andrew+netdev@...n.ch, anthony.l.nguyen@...el.com, davem@...emloft.net, 
	edumazet@...gle.com, ernesto@...tellotti.net,
 intel-wired-lan@...ts.osuosl.org, 	kuba@...nel.org,
 linux-kernel@...r.kernel.org, netdev@...r.kernel.org, 	pabeni@...hat.com,
 pmenzel@...gen.mpg.de, przemyslaw.kitszel@...el.com
Subject: Re: [Intel-wired-lan] [PATCH v2 1/1] ixgbe: Correct BASE-BX10
 compliance code

On Thu, 2024-11-14 at 19:50 +0000, Tore Amundsen wrote:
> The current value in the source code is 0x64, which appears to be a
> mix-up of hex and decimal values. A value of 0x64 (binary 01100100)
> incorrectly sets bit 2 (1000BASE-CX) and bit 5 (100BASE-FX) as well.
> ---
>  drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> index 14aa2ca51f70..81179c60af4e 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> @@ -40,7 +40,7 @@
>  #define IXGBE_SFF_1GBASESX_CAPABLE		0x1
>  #define IXGBE_SFF_1GBASELX_CAPABLE		0x2
>  #define IXGBE_SFF_1GBASET_CAPABLE		0x8
> -#define IXGBE_SFF_BASEBX10_CAPABLE		0x64
> +#define IXGBE_SFF_BASEBX10_CAPABLE		0x40
>  #define IXGBE_SFF_10GBASESR_CAPABLE		0x10
>  #define IXGBE_SFF_10GBASELR_CAPABLE		0x20
>  #define IXGBE_SFF_SOFT_RS_SELECT_MASK		0x8

LGMT.

Acked-by: Ernesto Castellotti <ernesto@...tellotti.net>

Kind regards,

Ernesto



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