netdev - Re: [PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1e902d79-5dad-4d12-a80e-464dbcf851c3@oss.qualcomm.com>
Date: Fri, 15 Nov 2024 20:11:48 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Yijie Yang <quic_yijiyang@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Richard Cochran <richardcochran@...il.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        quic_tingweiz@...cinc.com, quic_aiquny@...cinc.com
Subject: Re: [PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node

On 10.10.2024 5:05 AM, Yijie Yang wrote:
> Add ethqos ethernet controller node for QCS615 SoC.
> 
> Signed-off-by: Yijie Yang <quic_yijiyang@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 0d8fb557cf48..ba737cd89679 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -420,6 +420,33 @@ soc: soc@0 {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
>  
> +		ethernet: ethernet@...00 {
> +			compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos";
> +			reg = <0x0 0x20000 0x0 0x10000>,
> +			      <0x0 0x36000 0x0 0x100>;

Please pad the address part to 8 hex digits with leading zeroes

> +			reg-names = "stmmaceth", "rgmii";
> +
> +			clocks = <&gcc GCC_EMAC_AXI_CLK>,
> +			         <&gcc GCC_EMAC_SLV_AHB_CLK>,
> +			         <&gcc GCC_EMAC_PTP_CLK>,
> +			         <&gcc GCC_EMAC_RGMII_CLK>;
> +			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";

Please make this a vertical list, just like clocks

Konrad