netdev - Re: [PATCH v5 02/16] net: driver: stmmac: Extend CSR calc support

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Message-ID: <Zzy-SYu3AgwaHeOD@shell.armlinux.org.uk>
Date: Tue, 19 Nov 2024 16:35:21 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: jan.petrous@....nxp.com
Cc: Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Jose Abreu <joabreu@...opsys.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Vinod Koul <vkoul@...nel.org>,
	Richard Cochran <richardcochran@...il.com>,
	Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Emil Renner Berthing <kernel@...il.dk>,
	Minda Chen <minda.chen@...rfivetech.com>,
	Nicolas Ferre <nicolas.ferre@...rochip.com>,
	Claudiu Beznea <claudiu.beznea@...on.dev>,
	Iyappan Subramanian <iyappan@...amperecomputing.com>,
	Keyur Chudgar <keyur@...amperecomputing.com>,
	Quan Nguyen <quan@...amperecomputing.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Giuseppe Cavallaro <peppe.cavallaro@...com>,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org, linux-arm-msm@...r.kernel.org,
	imx@...ts.linux.dev, devicetree@...r.kernel.org,
	NXP S32 Linux Team <s32@....com>,
	Jacob Keller <jacob.e.keller@...el.com>
Subject: Re: [PATCH v5 02/16] net: driver: stmmac: Extend CSR calc support

On Tue, Nov 19, 2024 at 04:00:08PM +0100, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@....nxp.com>
> 
> Add support for CSR clock range up to 800 MHz.
> 
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@....nxp.com>
> Reviewed-by: Jacob Keller <jacob.e.keller@...el.com>

These look fine.

Doing the calculations:

100M / 42 = 2.38MHz
150M / 62 = 2.42MHz
35M / 16 = 2.19MHz
60M / 26 = 2.31MHz
250M / 102 = 2.45MHz
300M / 124 = 2.42MHz
500M / 204 = 2.45MHz
800M / 324 = 2.47MHz

Since the target MDC clock frequency is 2.5MHz, these all look
reasonable to what is in the comment for the new clock selection
values.

Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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