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Message-ID: <20241119182255.GA1967508-robh@kernel.org>
Date: Tue, 19 Nov 2024 12:22:55 -0600
From: Rob Herring <robh@...nel.org>
To: Daniel Machon <daniel.machon@...rochip.com>
Cc: UNGLinuxDriver@...rochip.com, Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Lars Povlsen <lars.povlsen@...rochip.com>,
Steen Hegelund <Steen.Hegelund@...rochip.com>,
Horatiu Vultur <horatiu.vultur@...rochip.com>,
Russell King <linux@...linux.org.uk>, jacob.e.keller@...el.com,
krzk+dt@...nel.org, conor+dt@...nel.org, devicetree@...r.kernel.org,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH net-next v3 8/8] dt-bindings: net: sparx5: document RGMII
delays
On Mon, Nov 18, 2024 at 02:00:54PM +0100, Daniel Machon wrote:
> The lan969x switch device supports two RGMII port interfaces that can be
> configured for MAC level rx and tx delays.
>
> Document two new properties {rx,tx}-internal-delay-ps. Make them
> required properties, if the phy-mode is one of: rgmii, rgmii_id,
> rgmii-rxid or rgmii-txid. Also specify accepted values.
Doesn't look like they are required to me.
>
> Signed-off-by: Daniel Machon <daniel.machon@...rochip.com>
> ---
> .../bindings/net/microchip,sparx5-switch.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
> index dedfad526666..2e9ef0f7bb4b 100644
> --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
> +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
> @@ -129,6 +129,24 @@ properties:
> minimum: 0
> maximum: 383
>
> + rx-internal-delay-ps:
> + description: |
Don't need '|' if there is not formatting to preserve.
> + RGMII Receive Clock Delay defined in pico seconds, used to select
> + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
> + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
> + any delay. The Default is no delay.
> + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
> + default: 0
> +
> + tx-internal-delay-ps:
> + description: |
> + RGMII Transmit Clock Delay defined in pico seconds, used to select
> + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
> + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
> + any delay. The Default is no delay.
> + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
> + default: 0
> +
> required:
> - reg
> - phys
>
> --
> 2.34.1
>
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