netdev - Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt lines

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Message-ID: <20241120-spirited-vulture-of-coffee-423adb-mkl@pengutronix.de>
Date: Wed, 20 Nov 2024 12:33:40 +0100
From: Marc Kleine-Budde <mkl@...gutronix.de>
To: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
Cc: Vincent Mailhol <mailhol.vincent@...adoo.fr>, 
	Andrew Lunn <andrew+netdev@...n.ch>, "David S . Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, 
	Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-can@...r.kernel.org, 
	netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	imx@...ts.linux.dev, NXP Linux Team <s32@....com>, 
	Christophe Lizzi <clizzi@...hat.com>, Alberto Ruiz <aruizrui@...hat.com>, 
	Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt
 lines

On 20.11.2024 13:02:56, Ciprian Marian Costea wrote:
> On 11/20/2024 12:54 PM, Marc Kleine-Budde wrote:
> > On 20.11.2024 12:47:02, Ciprian Marian Costea wrote:
> > > > > > > The mainline driver already handles the 2nd mailbox range (same
> > > > > > > 'flexcan_irq') is used. The only difference is that for the 2nd mailbox
> > > > > > > range a separate interrupt line is used.
> > > > > > 
> > > > > > AFAICS the IP core supports up to 128 mailboxes, though the driver only
> > > > > > supports 64 mailboxes. Which mailboxes do you mean by the "2nd mailbox
> > > > > > range"? What about mailboxes 64..127, which IRQ will them?
> > > > > 
> > > > > On S32G the following is the mapping between FlexCAN IRQs and mailboxes:
> > > > > - IRQ line X -> Mailboxes 0-7
> > > > > - IRQ line Y -> Mailboxes 8-127 (Logical OR of Message Buffer Interrupt
> > > > > lines 127 to 8)
> > > > > 
> > > > > By 2nd range, I was refering to Mailboxes 8-127.
> > > > 
> > > > Interesting, do you know why it's not symmetrical (0...63, 64...127)?
> > > > Can you point me to the documentation.
> > > 
> > > Unfortunately I do not know why such hardware integration decisions have
> > > been made.
> > > 
> > > Documentation for S32G3 SoC can be found on the official NXP website,
> > > here:
> > > https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g3-processors-for-vehicle-networking:S32G3
> > > 
> > > But please note that you need to setup an account beforehand.
> > 
> > I have that already, where is the mailbox to IRQ mapping described?
> > 
> > regards,
> > Marc
> > 
> 
> If you have successfully downloaded the Reference Manual for S32G2 or S32G3
> SoC, it should have attached an excel file describing all the interrupt
> mappings.

I downloaded the S32G3 Reference Manual:

| https://www.nxp.com/webapp/Download?colCode=RMS32G3

It's a pdf. Where can I find the execl file?

> In the excel file, if you search for 'FlexCAN_0' for example, you should be
> able to find IRQ lines 39 and 40 which correspond to Maiboxes 0-7 and 8-129
> (ored) previously discussed.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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