netdev - Re: [PATCH 2/3] can: flexcan: add NXP S32G2/S32G3 SoC support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c5bfa14b-ee2b-4d33-92b4-1bfdb0c843d6@oss.nxp.com>
Date: Wed, 20 Nov 2024 11:16:11 +0200
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
To: Marc Kleine-Budde <mkl@...gutronix.de>
Cc: Vincent Mailhol <mailhol.vincent@...adoo.fr>,
 Andrew Lunn <andrew+netdev@...n.ch>, "David S . Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-can@...r.kernel.org,
 netdev@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
 NXP Linux Team <s32@....com>, Christophe Lizzi <clizzi@...hat.com>,
 Alberto Ruiz <aruizrui@...hat.com>, Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH 2/3] can: flexcan: add NXP S32G2/S32G3 SoC support

On 11/20/2024 11:01 AM, Marc Kleine-Budde wrote:
> On 19.11.2024 10:10:52, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>>
>> Add device type data for S32G2/S32G3 SoC.
>>
>> FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
>> management is different. This initial S32G2/S32G3 SoC FlexCAN support
>> paves the road to address such differences.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> 
> If this flexcan integration has separate IRQ lines for Bus-Off and Error
> IRQs, please add the FLEXCAN_QUIRK_NR_IRQ_3 in this initial patch.
> 
> regards,
> Marc
> 

Indeed the FlexCAN integration on S32G has separate IRQ lines for 
Bus-Off and Error. I will add 'FLEXCAN_QUIRK_NR_IRQ_3' quirk into the 
initial S32G FlexCAN support commit as suggested, in V2.

Best Regards,
Ciprian