netdev - [PATCH net v1] mlxbf-gige: Support workaround for MDIO GPIO degradation bug

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Message-ID: <20241122224829.457786-1-asmaa@nvidia.com>
Date: Fri, 22 Nov 2024 22:48:27 +0000
From: Asmaa Mnebhi <asmaa@...dia.com>
To: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
	<pabeni@...hat.com>
CC: Asmaa Mnebhi <asmaa@...dia.com>, <netdev@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, David Thompson <davthompson@...dia.com>
Subject: [PATCH net v1] mlxbf-gige: Support workaround for MDIO GPIO degradation bug

From: asmaa <asmaa@...dia.com>

Once the BlueField-3 MDIO clock is enabled by software, it is expected
and intended for it to keep toggling. BlueField-3 has a hardware GPIO bug
where constant toggling at "high frequencies" will lead to GPIO
degradation.

The workaround suggested by the hardware team is to lower down the clock
frequency. That will increase the "life expectation" of the GPIO.
The lowest possible frequency we can achieve is 1.09Mhz by setting
mdio_period = 0xFF.

Fixes: f92e1869d74e ("Add Mellanox BlueField Gigabit Ethernet driver")
Signed-off-by: Asmaa Mnebhi <asmaa@...dia.com>
---
 .../ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
index 654190263535..d6dd36ab599e 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
@@ -96,6 +96,7 @@ static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = {
 #define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
 #define MLXBF_GIGE_MDIO_COREPLL_CONST  16384ULL
 #define MLXBF_GIGE_MDC_CLK_NS          400
+#define MLXBF_GIGE_BF3_MDIO_PERIOD     0xFF
 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4
 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8
 #define MLXBF_GIGE_MDIO_CORE_F_SHIFT   0
@@ -178,9 +179,16 @@ static u8 mdio_period_map(struct mlxbf_gige *priv)
 	u8 mdio_period;
 	u64 i1clk;
 
-	i1clk = calculate_i1clk(priv);
-
-	mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
+	/* The MDIO clock frequency need to be set as low as possible to avoid
+	 * a BF3 hardware GPIO degradation. The lowest frequency can be achieved
+	 * by setting MdioPeriod = 0xFF.
+	 */
+	if (priv->hw_version == MLXBF_GIGE_VERSION_BF3) {
+		mdio_period = MLXBF_GIGE_BF3_MDIO_PERIOD;
+	} else {
+		i1clk = calculate_i1clk(priv);
+		mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
+	}
 
 	return mdio_period;
 }
-- 
2.47.0