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Message-ID: <Z06mKpcvBO23RSx+@lsv051416.swis.nl-cdc01.nxp.com>
Date: Tue, 3 Dec 2024 07:33:14 +0100
From: Jan Petrous <jan.petrous@....nxp.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
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Krzysztof Kozlowski <krzk+dt@...nel.org>,
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Subject: Re: [PATCH net-next v7 14/15] net: stmmac: dwmac-s32: add basic NXP
S32G/S32R glue driver
On Tue, Dec 03, 2024 at 12:43:58AM +0100, Andrew Lunn wrote:
> > +static int s32_gmac_init(struct platform_device *pdev, void *priv)
> > +{
> > + struct s32_priv_data *gmac = priv;
> > + int ret;
> > +
> > + ret = clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M);
> > + if (!ret)
> > + ret = clk_prepare_enable(gmac->tx_clk);
> > +
> > + if (ret) {
> > + dev_err(&pdev->dev, "Can't set tx clock\n");
> > + return ret;
> > + }
>
> The ordering is a bit odd here. Normally you would test each operation
> individually for errors. So:
>
> ret = clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M);
> if (ret) {
> dev_err(&pdev->dev, "Can't set tx clock\n");
> return ret;
> }
> ret = clk_prepare_enable(gmac->tx_clk);
> if (ret) {
> dev_err(&pdev->dev, "Can't enable tx clock\n");
> return ret;
> }
>
Thanks for it. The ordering is incorrect, agree. I will fix it in v8.
>
> > +
> > + ret = clk_prepare_enable(gmac->rx_clk);
> > + if (ret) {
> > + clk_disable_unprepare(gmac->tx_clk);
> > + dev_err(&pdev->dev, "Can't set rx clock\n");
> > + return ret;
> > + }
>
> Is there no need to set the TX clock rate?
>
Do you mean RX clock, right? Yes, I'll add it in v8 too.
BR.
/Jan
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