netdev - Re: [PATCH net-next] e1000e: Fix real-time violations on link up

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Message-ID: <06edcab8-280d-4397-8df2-58a35eb094ec@engleder-embedded.com>
Date: Wed, 4 Dec 2024 21:21:49 +0100
From: Gerhard Engleder <gerhard@...leder-embedded.com>
To: Przemek Kitszel <przemyslaw.kitszel@...el.com>
Cc: anthony.l.nguyen@...el.com, andrew+netdev@...n.ch,
 netdev@...r.kernel.org, davem@...emloft.net, kuba@...nel.org,
 edumazet@...gle.com, pabeni@...hat.com, Gerhard Engleder <eg@...a.com>,
 Vitaly Lifshits <vitaly.lifshits@...el.com>,
 "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
Subject: Re: [PATCH net-next] e1000e: Fix real-time violations on link up

On 04.12.24 11:10, Przemek Kitszel wrote:
> On 12/3/24 21:28, Gerhard Engleder wrote:
>> From: Gerhard Engleder <eg@...a.com>
>>
>> From: Gerhard Engleder <eg@...a.com>
> 
> duplicated From: line

Nervous fingers, sorry, will be fixed.

>>
>> Link down and up triggers update of MTA table. This update executes many
>> PCIe writes and a final flush. Thus, PCIe will be blocked until all 
>> writes
>> are flushed. As a result, DMA transfers of other targets suffer from 
>> delay
>> in the range of 50us. This results in timing violations on real-time
>> systems during link down and up of e1000e.
>>
>> A flush after a low enough number of PCIe writes eliminates the delay
>> but also increases the time needed for MTA table update. The following
>> measurements were done on i3-2310E with e1000e for 128 MTA table entries:
>>
>> Single flush after all writes: 106us
>> Flush after every write:       429us
>> Flush after every 2nd write:   266us
>> Flush after every 4th write:   180us
>> Flush after every 8th write:   141us
>> Flush after every 16th write:  121us
>>
>> A flush after every 8th write delays the link up by 35us and the
>> negative impact to DMA transfers of other targets is still tolerable.
>>
>> Execute a flush after every 8th write. This prevents overloading the
>> interconnect with posted writes. As this also increases the time spent 
>> for
>> MTA table update considerable this change is limited to PREEMPT_RT.
> 
> hmm, why to limit this to PREEMPT_RT, the change sounds resonable also
> for the standard kernel, at last for me
> (perhaps with every 16th write instead)

As Andrew argumented similar, I will remove the PREEMPT_RT dependency
with the next version. This is not the hot path, so the additional delay
of <<1ms for boot and interface up is negligible.

> with that said, I'm fine with this patch as is too
> 
>>
>> Signed-off-by: Gerhard Engleder <eg@...a.com>
> 
> would be good to add link to your RFC
> https://lore.kernel.org/netdev/f8fe665a-5e6c-4f95-b47a-2f3281aa0e6c@lunn.ch/T/
> 
> and also CC Vitaly who participated there (done),
> same for IWL mailing list (also CCd), and use iwl-next tag for your
> future contributions to intel ethernet

Will be done.

Thank you for the review!

Gerhard