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Message-ID: <96493972-2f1d-cb11-a578-e56b3f067ea2@amd.com>
Date: Mon, 9 Dec 2024 09:22:13 +0000
From: Alejandro Lucero Palau <alucerop@....com>
To: Fan Ni <nifan.cxl@...il.com>, alejandro.lucero-palau@....com
Cc: linux-cxl@...r.kernel.org, netdev@...r.kernel.org,
dan.j.williams@...el.com, martin.habets@...inx.com, edward.cree@....com,
davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com,
edumazet@...gle.com, dave.jiang@...el.com
Subject: Re: [PATCH v6 15/28] cxl: define a driver interface for HPA free
space enumeration
On 12/6/24 19:48, Fan Ni wrote:
> On Mon, Dec 02, 2024 at 05:12:09PM +0000, alejandro.lucero-palau@....com wrote:
>> From: Alejandro Lucero <alucerop@....com>
>>
>> CXL region creation involves allocating capacity from device DPA
>> (device-physical-address space) and assigning it to decode a given HPA
>> (host-physical-address space). Before determining how much DPA to
>> allocate the amount of available HPA must be determined. Also, not all
>> HPA is create equal, some specifically targets RAM, some target PMEM,
>> some is prepared for device-memory flows like HDM-D and HDM-DB, and some
>> is host-only (HDM-H).
>>
>> Wrap all of those concerns into an API that retrieves a root decoder
>> (platform CXL window) that fits the specified constraints and the
>> capacity available for a new region.
>>
>> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> Co-developed-by: Dan Williams <dan.j.williams@...el.com>
>> ---
>> drivers/cxl/core/region.c | 145 ++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxl.h | 3 +
>> include/cxl/cxl.h | 8 +++
>> 3 files changed, 156 insertions(+)
>>
> ...
>> + /*
>> + * Walk the root decoder resource range relying on cxl_region_rwsem to
>> + * preclude sibling arrival/departure and find the largest free space
>> + * gap.
>> + */
>> + lockdep_assert_held_read(&cxl_region_rwsem);
>> + max = 0;
>> + res = cxlrd->res->child;
>> + if (!res)
>> + max = resource_size(cxlrd->res);
>> + else
>> + max = 0;
>> +
>> + for (prev = NULL; res; prev = res, res = res->sibling) {
>> + struct resource *next = res->sibling;
>> + resource_size_t free = 0;
>> +
>> + if (!prev && res->start > cxlrd->res->start) {
>> + free = res->start - cxlrd->res->start;
>> + max = max(free, max);
>> + }
>> + if (prev && res->start > prev->end + 1) {
>> + free = res->start - prev->end + 1;
> Should it be
> free = res->start - (prev->end + 1);
> ?
>> + max = max(free, max);
>> + }
>> + if (next && res->end + 1 < next->start) {
>> + free = next->start - res->end + 1;
> free = next->start - (res->end + 1);
>
> Fan
I do not think it is necessary except for legibility.
The only case would be res->end or prev->end above being from a resource
defined with zero size, implying being all 1s as it would be initialized
with 0 - 1 for an unsigned variable.
But I think we can be sure no resource with size 0 will be in the list
walked ... But maybe we could make a sanity check here.
I'll add that.
Thanks!
>> + max = max(free, max);
>> + }
>> + if (!next && res->end + 1 < cxlrd->res->end + 1) {
>> + free = cxlrd->res->end + 1 - res->end + 1;
>> + max = max(free, max);
>> + }
>> + }
>> +
>> + dev_dbg(CXLRD_DEV(cxlrd), "%s, found %pa bytes of free space\n",
>> + __func__, &max);
>> + if (max > ctx->max_hpa) {
>> + if (ctx->cxlrd)
>> + put_device(CXLRD_DEV(ctx->cxlrd));
>> + get_device(CXLRD_DEV(cxlrd));
>> + ctx->cxlrd = cxlrd;
>> + ctx->max_hpa = max;
>> + dev_dbg(CXLRD_DEV(cxlrd), "%s, found %pa bytes of free space\n",
>> + __func__, &max);
>> + }
>> + return 0;
>> +}
>> +
>> +/**
>> + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints
>> + * @endpoint: an endpoint that is mapped by the returned decoder
>> + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B]
>> + * @max_avail_contig: output parameter of max contiguous bytes available in the
>> + * returned decoder
>> + *
>> + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available given
>> + * in (@max_avail_contig))' is a point in time snapshot. If by the time the
>> + * caller goes to use this root decoder's capacity the capacity is reduced then
>> + * caller needs to loop and retry.
>> + *
>> + * The returned root decoder has an elevated reference count that needs to be
>> + * put with put_device(cxlrd_dev(cxlrd)). Locking context is with
>> + * cxl_{acquire,release}_endpoint(), that ensures removal of the root decoder
>> + * does not race.
>> + */
>> +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd,
>> + unsigned long flags,
>> + resource_size_t *max_avail_contig)
>> +{
>> + struct cxl_port *endpoint = cxlmd->endpoint;
>> + struct cxlrd_max_context ctx = {
>> + .host_bridge = endpoint->host_bridge,
>> + .flags = flags,
>> + };
>> + struct cxl_port *root_port;
>> + struct cxl_root *root __free(put_cxl_root) = find_cxl_root(endpoint);
>> +
>> + if (!is_cxl_endpoint(endpoint)) {
>> + dev_dbg(&endpoint->dev, "hpa requestor is not an endpoint\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + if (!root) {
>> + dev_dbg(&endpoint->dev, "endpoint can not be related to a root port\n");
>> + return ERR_PTR(-ENXIO);
>> + }
>> +
>> + root_port = &root->port;
>> + down_read(&cxl_region_rwsem);
>> + device_for_each_child(&root_port->dev, &ctx, find_max_hpa);
>> + up_read(&cxl_region_rwsem);
>> +
>> + if (!ctx.cxlrd)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + *max_avail_contig = ctx.max_hpa;
>> + return ctx.cxlrd;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_get_hpa_freespace, CXL);
>> +
>> static ssize_t size_store(struct device *dev, struct device_attribute *attr,
>> const char *buf, size_t len)
>> {
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 22e787748d79..57d6dda3fb4a 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -785,6 +785,9 @@ static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport,
>> struct cxl_decoder *to_cxl_decoder(struct device *dev);
>> struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
>> struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
>> +
>> +#define CXLRD_DEV(cxlrd) (&(cxlrd)->cxlsd.cxld.dev)
>> +
>> struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
>> bool is_root_decoder(struct device *dev);
>> bool is_switch_decoder(struct device *dev);
>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>> index 26d7735b5f31..eacd5e5e6fe8 100644
>> --- a/include/cxl/cxl.h
>> +++ b/include/cxl/cxl.h
>> @@ -7,6 +7,10 @@
>> #include <linux/ioport.h>
>> #include <linux/pci.h>
>>
>> +#define CXL_DECODER_F_RAM BIT(0)
>> +#define CXL_DECODER_F_PMEM BIT(1)
>> +#define CXL_DECODER_F_TYPE2 BIT(2)
>> +
>> enum cxl_resource {
>> CXL_RES_DPA,
>> CXL_RES_RAM,
>> @@ -47,4 +51,8 @@ int cxl_release_resource(struct cxl_dev_state *cxlds, enum cxl_resource type);
>> void cxl_set_media_ready(struct cxl_dev_state *cxlds);
>> struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
>> struct cxl_dev_state *cxlds);
>> +struct cxl_port;
>> +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd,
>> + unsigned long flags,
>> + resource_size_t *max);
>> #endif
>> --
>> 2.17.1
>>
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