netdev - Re: KSZ8795 not detected at start to boot from NFS

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Message-ID: <vuslt6lyxgfyswtpymtu5yklflzqs5f2l2yqtzlypnyqe6llkk@yz3eakhmctsq>
Date: Tue, 10 Dec 2024 22:21:07 +0100
From: Jörg Sommer <joerg@...so.de>
To: Andrew Lunn <andrew@...n.ch>
Cc: Christian Eggers <ceggers@...i.de>, netdev@...r.kernel.org
Subject: Re: KSZ8795 not detected at start to boot from NFS

Andrew Lunn schrieb am Di 10. Dez, 18:41 (+0100):
> > So I think it's a timing problem: the ksz8795 isn't ready after the SPI
> > reset, when the chip ID gets read, and this causes the probing to stop.
> 
> Is there anything in the datasheet about reset timing? 

Not exactly. On page 127 is a diagram about resetting the chip.

https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8795CLX-Data-Sheet-DS00002112.pdf

Here's a commit that contains a calculation and determines 100ms.

commit 1aa4ee0ec7fe929bd46ae20d9457f0a242115643
Author: Marek Vasut <marex@...x.de>
Date:   Wed Jan 20 04:05:02 2021 +0100

    net: dsa: microchip: Adjust reset release timing to match reference reset circuit

    commit 1c45ba93d34cd6af75228f34d0675200c81738b5 upstream.

    KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
    circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
    resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
    rise enough to release the reset.

    For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
                        VDDIO - VIH
      t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
                           VDDIO
    so we need ~95 ms for the reset to really de-assert, and then the
    original 100us for the switch itself to come out of reset. Simply
    msleep() for 100 ms which fits the constraint with a bit of extra
    space.


Jörg

-- 
„Dass man etwas durchdringen kann, wenn man es durchschaut
 hat, ist der Irrtum der Fliege an der Fensterscheibe.“ (Nietzsche)

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