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Message-ID: <81786f5a-42b0-2e5a-c2d6-bfd93b366d97@amd.com>
Date: Fri, 27 Dec 2024 07:07:59 +0000
From: Alejandro Lucero Palau <alucerop@....com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>,
alejandro.lucero-palau@....com
Cc: linux-cxl@...r.kernel.org, netdev@...r.kernel.org,
dan.j.williams@...el.com, martin.habets@...inx.com, edward.cree@....com,
davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com,
edumazet@...gle.com, dave.jiang@...el.com
Subject: Re: [PATCH v8 03/27] cxl: add capabilities field to cxl_dev_state and
cxl_port
On 12/24/24 17:08, Jonathan Cameron wrote:
> On Mon, 16 Dec 2024 16:10:18 +0000
> <alejandro.lucero-palau@....com> wrote:
>
>> From: Alejandro Lucero <alucerop@....com>
>>
>> Type2 devices have some Type3 functionalities as optional like an mbox
>> or an hdm decoder, and CXL core needs a way to know what an CXL accelerator
>> implements.
>>
>> Add a new field to cxl_dev_state for keeping device capabilities as
>> discovered during initialization. Add same field to cxl_port as registers
>> discovery is also used during port initialization.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
>> Reviewed-by: Fan Ni <fan.ni@...sung.com>
> Use set_bit() not dereference and |= to set the bits in the bitmap
> At that point you can void need to force the length of the bitmap.
>
> Jonathan
>
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index 59cb35b40c7e..ac3a27c6e442 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -113,11 +118,12 @@ EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, "CXL");
>> * @dev: Host device of the @base mapping
>> * @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
>> * @map: Map object describing the register block information found
>> + * @caps: capabilities to be set when discovered
>> *
>> * Probe for device register information and return it in map object.
>> */
>> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>> - struct cxl_device_reg_map *map)
>> + struct cxl_device_reg_map *map, unsigned long *caps)
>> {
>> int cap, cap_count;
>> u64 cap_array;
>> @@ -146,10 +152,12 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>> case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
>> dev_dbg(dev, "found Status capability (0x%x)\n", offset);
>> rmap = &map->status;
>> + *caps |= BIT(CXL_DEV_CAP_DEV_STATUS);
>> break;
>> case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
>> dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
>> rmap = &map->mbox;
>> + *caps |= BIT(CXL_DEV_CAP_MAILBOX_PRIMARY);
>> break;
>> case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
>> dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
>> @@ -157,6 +165,7 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>> case CXLDEV_CAP_CAP_ID_MEMDEV:
>> dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
>> rmap = &map->memdev;
>> + *caps |= BIT(CXL_DEV_CAP_MEMDEV);
> Ah. That would will be why the 64 below. use set_bit() for these, not a dereference.
>
Makes sense.
I'll do it.
>> break;
>> default:
>> if (cap_id >= 0x8000)
>> @@ -421,7 +430,7 @@ static void cxl_unmap_regblock(struct cxl_register_map *map)
>> map->base = NULL;
>> }
>>
>> -static int cxl_probe_regs(struct cxl_register_map *map)
>> +static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps)
>> {
>> struct cxl_component_reg_map *comp_map;
>> struct cxl_device_reg_map *dev_map;
>> @@ -431,12 +440,12 @@ static int cxl_probe_regs(struct cxl_register_map *map)
>> switch (map->reg_type) {
>> case CXL_REGLOC_RBI_COMPONENT:
>> comp_map = &map->component_map;
>> - cxl_probe_component_regs(host, base, comp_map);
>> + cxl_probe_component_regs(host, base, comp_map, caps);
>> dev_dbg(host, "Set up component registers\n");
>> break;
>> case CXL_REGLOC_RBI_MEMDEV:
>> dev_map = &map->device_map;
>> - cxl_probe_device_regs(host, base, dev_map);
>> + cxl_probe_device_regs(host, base, dev_map, caps);
>> if (!dev_map->status.valid || !dev_map->mbox.valid ||
>> !dev_map->memdev.valid) {
>> dev_err(host, "registers not found: %s%s%s\n",
>> @@ -455,7 +464,7 @@ static int cxl_probe_regs(struct cxl_register_map *map)
>> return 0;
>> }
>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>> index 19e5d883557a..f656fcd4945f 100644
>> --- a/include/cxl/cxl.h
>> +++ b/include/cxl/cxl.h
>> @@ -12,6 +12,25 @@ enum cxl_resource {
>> CXL_RES_PMEM,
>> };
>>
>> +/* Capabilities as defined for:
>> + *
>> + * Component Registers (Table 8-22 CXL 3.1 specification)
>> + * Device Registers (8.2.8.2.1 CXL 3.1 specification)
>> + *
>> + * and currently being used for kernel CXL support.
>> + */
>> +
>> +enum cxl_dev_cap {
>> + /* capabilities from Component Registers */
>> + CXL_DEV_CAP_RAS,
>> + CXL_DEV_CAP_HDM,
>> + /* capabilities from Device Registers */
>> + CXL_DEV_CAP_DEV_STATUS,
>> + CXL_DEV_CAP_MAILBOX_PRIMARY,
>> + CXL_DEV_CAP_MEMDEV,
>> + CXL_MAX_CAPS = 64
> Why set it to 64? All the bitmaps etc will autosize so
> you just need to ensure you use correct set_bit() and test_bit()
> that are happy dealing with bitmaps of multiple longs.
>
Initially it was set to 32, but DECLARE_BITMAP uses unsigned long, so
for initializing/zeroing the locally allocated bitmap in some functions,
bitmap_clear had to use sizeof for the size, and I was suggested to
define CXL_MAX_CAPS to 64 and use it instead, what seems cleaner.
>> +};
>> +
>> struct cxl_dev_state *cxl_accel_state_create(struct device *dev);
>>
>> void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec);
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