netdev - Re: [PATCH net-next v2 03/14] net: ethernet: qualcomm: Add PPE driver for IPQ9574 SoC

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Message-ID: <6a980f4f-d27f-40a5-99f1-6f7c90949b6a@quicinc.com>
Date: Thu, 9 Jan 2025 22:18:13 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Christophe JAILLET <christophe.jaillet@...adoo.fr>,
        Andrew Lunn
	<andrew+netdev@...n.ch>,
        "David S. Miller" <davem@...emloft.net>,
        "Eric
 Dumazet" <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
	<pabeni@...hat.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Lei Wei
	<quic_leiwei@...cinc.com>,
        Suruchi Agarwal <quic_suruchia@...cinc.com>,
        Pavithra R <quic_pavir@...cinc.com>, Simon Horman <horms@...nel.org>,
        Jonathan Corbet <corbet@....net>, Kees Cook <kees@...nel.org>,
        "Gustavo A. R.
 Silva" <gustavoars@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>, <linux-hardening@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_linchen@...cinc.com>,
        <srinivas.kandagatla@...aro.org>, <bartosz.golaszewski@...aro.org>,
        <john@...ozen.org>
Subject: Re: [PATCH net-next v2 03/14] net: ethernet: qualcomm: Add PPE driver
 for IPQ9574 SoC



On 1/9/2025 3:19 AM, Christophe JAILLET wrote:
> Le 08/01/2025 à 14:47, Luo Jie a écrit :
>> The PPE (Packet Process Engine) hardware block is available
>> on Qualcomm IPQ SoC that support PPE architecture, such as
>> IPQ9574.
>>
>> The PPE in IPQ9574 includes six integrated ethernet MAC
>> (for 6 PPE ports), buffer management, queue management and
>> scheduler functions. The MACs can connect with the external
>> PHY or switch devices using the UNIPHY PCS block available
>> in the SoC.
>>
>> The PPE also includes various packet processing offload
>> capabilities such as L3 routing and L2 bridging, VLAN and
>> tunnel processing offload. It also includes Ethernet DMA
>> function for transferring packets between ARM cores and
>> PPE ethernet ports.
>>
>> This patch adds the base source files and Makefiles for
>> the PPE driver such as platform driver registration,
>> clock initialization, and PPE reset routines.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
> 
> ...
> 
>> +static int qcom_ppe_probe(struct platform_device *pdev)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct ppe_device *ppe_dev;
>> +    void __iomem *base;
>> +    int ret, num_icc;
>> +
>> +    num_icc = ARRAY_SIZE(ppe_icc_data);
>> +    ppe_dev = devm_kzalloc(dev, struct_size(ppe_dev, icc_paths, 
>> num_icc),
>> +                   GFP_KERNEL);
>> +    if (!ppe_dev)
>> +        return dev_err_probe(dev, -ENOMEM, "PPE alloc memory failed\n");
> 
> Usually, no error message in logged in case of devm_kzalloc().
> It is already loud enough.
> 

OK. Will remove.

>> +
>> +    base = devm_platform_ioremap_resource(pdev, 0);
>> +    if (IS_ERR(base))
>> +        return dev_err_probe(dev, PTR_ERR(base), "PPE ioremap 
>> failed\n");
>> +
>> +    ppe_dev->regmap = devm_regmap_init_mmio(dev, base, 
>> &regmap_config_ipq9574);
>> +    if (IS_ERR(ppe_dev->regmap))
>> +        return dev_err_probe(dev, PTR_ERR(ppe_dev->regmap),
>> +                     "PPE initialize regmap failed\n");
>> +    ppe_dev->dev = dev;
>> +    ppe_dev->clk_rate = PPE_CLK_RATE;
>> +    ppe_dev->num_ports = PPE_PORT_MAX;
>> +    ppe_dev->num_icc_paths = num_icc;
>> +
>> +    ret = ppe_clock_init_and_reset(ppe_dev);
>> +    if (ret)
>> +        return dev_err_probe(dev, ret, "PPE clock config failed\n");
>> +
>> +    platform_set_drvdata(pdev, ppe_dev);
>> +
>> +    return 0;
>> +}
>> +
>> +static const struct of_device_id qcom_ppe_of_match[] = {
>> +    { .compatible = "qcom,ipq9574-ppe" },
>> +    {},
> 
> The ending comma after a terminator like that is not needed.

Will remove it.

> 
>> +};
> 
> ...
> 
> CJ
>