netdev - [PATCH net-next] net: ethernet: ti: am65-cpsw: VLAN-aware CPSW only if !DSA

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Message-ID: <20250110092624.287209-1-alexander.sverdlin@siemens.com>
Date: Fri, 10 Jan 2025 10:26:21 +0100
From: "A. Sverdlin" <alexander.sverdlin@...mens.com>
To: Siddharth Vadapalli <s-vadapalli@...com>,
	netdev@...r.kernel.org
Cc: Alexander Sverdlin <alexander.sverdlin@...mens.com>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	Roger Quadros <rogerq@...nel.org>,
	Chintan Vankar <c-vankar@...com>,
	Julien Panis <jpanis@...libre.com>
Subject: [PATCH net-next] net: ethernet: ti: am65-cpsw: VLAN-aware CPSW only if !DSA

From: Alexander Sverdlin <alexander.sverdlin@...mens.com>

Only configure VLAN-aware CPSW mode if no port is used as DSA CPU port.
VLAN-aware mode interferes with some DSA tagging schemes and makes stacking
DSA switches downstream of CPSW impossible. Previous attempts to address
the issue linked below.

Link: https://lore.kernel.org/netdev/20240227082815.2073826-1-s-vadapalli@ti.com/
Link: https://lore.kernel.org/linux-arm-kernel/4699400.vD3TdgH1nR@localhost/
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@...mens.com>
---
 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index dcb6662b473d..e445acb29e16 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -32,6 +32,7 @@
 #include <linux/dma/ti-cppi5.h>
 #include <linux/dma/k3-udma-glue.h>
 #include <net/page_pool/helpers.h>
+#include <net/dsa.h>
 #include <net/switchdev.h>
 
 #include "cpsw_ale.h"
@@ -724,13 +725,23 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)
 	u32 val, port_mask;
 	struct page *page;
 
+	/* Control register */
+	val = AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
+	      AM65_CPSW_CTL_P0_RX_PAD;
+	for (port_idx = 0; port_idx < common->port_num; port_idx++) {
+		struct am65_cpsw_port *port = &common->ports[port_idx];
+
+		if (netdev_uses_dsa(port->ndev))
+			break;
+	}
+	/* VLAN aware CPSW mode is incompatible with some DSA tagging schemes */
+	if (port_idx == common->port_num)
+		val |= AM65_CPSW_CTL_VLAN_AWARE;
+	writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
+
 	if (common->usage_count)
 		return 0;
 
-	/* Control register */
-	writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
-	       AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD,
-	       common->cpsw_base + AM65_CPSW_REG_CTL);
 	/* Max length register */
 	writel(AM65_CPSW_MAX_PACKET_SIZE,
 	       host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
-- 
2.47.1