netdev - Re: [PATCH net-next 07/10] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings

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Message-ID: <Z4TO2fPPhvcPmPyb@mev-dev.igk.intel.com>
Date: Mon, 13 Jan 2025 09:29:13 +0100
From: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
To: Michael Chan <michael.chan@...adcom.com>
Cc: davem@...emloft.net, netdev@...r.kernel.org, edumazet@...gle.com,
	kuba@...nel.org, pabeni@...hat.com, andrew+netdev@...n.ch,
	pavan.chebbi@...adcom.com, andrew.gospodarek@...adcom.com,
	somnath.kotur@...adcom.com,
	Hongguang Gao <hongguang.gao@...adcom.com>,
	Ajit Khaparde <ajit.khaparde@...adcom.com>
Subject: Re: [PATCH net-next 07/10] bnxt_en: Pass NQ ID to the FW when
 allocating RX/RX AGG rings

On Sun, Jan 12, 2025 at 10:39:24PM -0800, Michael Chan wrote:
> Newer firmware can use the NQ ring ID associated with each RX/RX AGG
> ring to enable PCIe Steering Tags on P5_PLUS chips.  When allocating
> RX/RX AGG rings, pass along NQ ring ID for the firmware to use.  This
> information helps optimize DMA writes by directing them to the cache
> closer to the CPU consuming the data, potentially improving the
> processing speed.  This change is backward-compatible with older
> firmware, which will simply disregard the information.
> 
> Reviewed-by: Hongguang Gao <hongguang.gao@...adcom.com>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@...adcom.com>
> Signed-off-by: Andy Gospodarek <andrew.gospodarek@...adcom.com>
> Signed-off-by: Michael Chan <michael.chan@...adcom.com>
> ---
>  drivers/net/ethernet/broadcom/bnxt/bnxt.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> index c862250d3b77..30a57bbc407c 100644
> --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> @@ -6922,7 +6922,8 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type,
>  				       struct bnxt_ring_struct *ring)
>  {
>  	struct bnxt_ring_grp_info *grp_info = &bp->grp_info[ring->grp_idx];
> -	u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;
> +	u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID |
> +		      RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID;
>  
>  	if (ring_type == HWRM_RING_ALLOC_AGG) {
>  		req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
> @@ -6936,6 +6937,7 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type,
>  				cpu_to_le16(RING_ALLOC_REQ_FLAGS_RX_SOP_PAD);
>  	}
>  	req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
> +	req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
>  	req->enables |= cpu_to_le32(enables);
>  }
>  
> -- 
> 2.30.1

Reviewed-by: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>