netdev - Re: [PATCH net 1/2] net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5

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Message-ID: <Z4fJjf4nyiNyRus_@shell.armlinux.org.uk>
Date: Wed, 15 Jan 2025 14:43:25 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: netdev@...r.kernel.org, Jose Abreu <Jose.Abreu@...opsys.com>,
	Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Voon Weifeng <weifeng.voon@...el.com>,
	Michael Sit Wei Hong <michael.wei.hong.sit@...el.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH net 1/2] net: pcs: xpcs: fix DW_VR_MII_DIG_CTRL1_2G5_EN
 bit being set for 1G SGMII w/o inband

On Tue, Jan 14, 2025 at 06:47:20PM +0200, Vladimir Oltean wrote:
> On a port with SGMII fixed-link at SPEED_1000, DW_VR_MII_DIG_CTRL1 gets
> set to 0x2404. This is incorrect, because bit 2 (DW_VR_MII_DIG_CTRL1_2G5_EN)
> is set.
> 
> It comes from the previous write to DW_VR_MII_AN_CTRL, because the "val"
> variable is reused and is dirty. Actually, its value is 0x4, aka
> FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII).
> 
> Resolve the issue by clearing "val" to 0 when writing to a new register.
> After the fix, the register value is 0x2400.
> 
> Prior to the blamed commit, when the read-modify-write was open-coded,
> the code saved the content of the DW_VR_MII_DIG_CTRL1 register in the
> "ret" variable.
> 
> Fixes: ce8d6081fcf4 ("net: pcs: xpcs: add _modify() accessors")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>

Good catch!

Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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