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Message-ID: <20250115155354.0acdacc7@fedora.home>
Date: Wed, 15 Jan 2025 15:53:54 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>, Andrew Lunn
<andrew+netdev@...n.ch>, Bryan Whitehead <bryan.whitehead@...rochip.com>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com, Marcin Wojtas
<marcin.s.wojtas@...il.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
netdev@...r.kernel.org, Paolo Abeni <pabeni@...hat.com>, Simon Horman
<horms@...nel.org>, UNGLinuxDriver@...rochip.com, Vladimir Oltean
<olteanv@...il.com>
Subject: Re: [PATCH RFC net-next 06/10] net: mvpp2: add EEE implementation
Hello Russell,
On Tue, 14 Jan 2025 14:02:29 +0000
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk> wrote:
> Add EEE support for mvpp2, using phylink's EEE implementation, which
> means we just need to implement the two methods for LPI control, and
> with the initial configuration. Only SGMII mode is supported, so only
> 100M and 1G speeds.
>
> Disabling LPI requires clearing a single bit. Enabling LPI needs a full
> configuration of several values, as the timer values are dependent on
> the MAC operating speed.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
> --
> v3: split LPI timer limit and validation into separate patches
> ---
> drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 5 ++
> .../net/ethernet/marvell/mvpp2/mvpp2_main.c | 86 +++++++++++++++++++
> 2 files changed, 91 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index 9e02e4367bec..364d038da7ea 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -481,6 +481,11 @@
> #define MVPP22_GMAC_INT_SUM_MASK 0xa4
> #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
> #define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
> +#define MVPP2_GMAC_LPI_CTRL0 0xc0
> +#define MVPP2_GMAC_LPI_CTRL0_TS_MASK GENMASK(8, 8)
I think this should be GENMASK(15, 8) :)
The rest looks good to me,
Thanks,
Maxime
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