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Message-ID: <20250121-dts_qcs615-v3-4-fa4496950d8a@quicinc.com>
Date: Tue, 21 Jan 2025 15:54:56 +0800
From: Yijie Yang <quic_yijiyang@...cinc.com>
To: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller"
<davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
Richard Cochran <richardcochran@...il.com>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>,
Yijie Yang
<quic_yijiyang@...cinc.com>
Subject: [PATCH v3 4/4] arm64: dts: qcom: qcs615-ride: Enable ethernet node
Enable the ethernet node, add the phy node and pinctrl for ethernet. This
change is necessary to support ethernet functionality on this board.
Signed-off-by: Yijie Yang <quic_yijiyang@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 104 +++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 2b5aa3c66867676bda59ff82b902b6e4974126f8..2d201b5d09a79613364f0e514858dd30b25706a9 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -211,6 +211,59 @@ vreg_l17a: ldo17 {
};
};
+ðernet {
+ pinctrl-0 = <ðernet_defaults>;
+ pinctrl-names = "default";
+
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-id";
+
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy: phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x7>;
+
+ interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
+ device_type = "ethernet-phy";
+ reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+ };
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ snps,tx-sched-wrr;
+
+ queue0 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ };
+ };
+};
+
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
@@ -278,6 +331,57 @@ &sdhc_2 {
status = "okay";
};
+&tlmm {
+ ethernet_defaults: ethernet-defaults-state {
+ mdc-pins {
+ pins = "gpio113";
+ function = "rgmii";
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio114";
+ function = "rgmii";
+ bias-pull-up;
+ };
+
+ rgmii-rx-pins {
+ pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112";
+ function = "rgmii";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ rgmii-tx-pins {
+ pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97";
+ function = "rgmii";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+
+ phy-intr-pins {
+ pins = "gpio121";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ phy-reset-pins {
+ pins = "gpio104";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+
+ pps-pins {
+ pins = "gpio91";
+ function = "rgmii";
+ bias-disable;
+ drive-strength = <8>;
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.34.1
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