From: "Russell King (Oracle)" Subject: [PATCH net-next 3/4] net: xpcs: add support for configuring width of 10/100M MII connection When in SGMII mode, the hardware can be configured to use either 4-bit or 8-bit MII connection. Currently, we don't change this bit for most implementations with the exception of TXGBE requiring 8-bit. Move this decision to the creation code and act on it when configuring SGMII. Signed-off-by: Russell King (Oracle) --- drivers/net/pcs/pcs-xpcs.c | 20 +++++++++++++++----- drivers/net/pcs/pcs-xpcs.h | 8 ++++++++ 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 477a3a20f860..75ed8d535de2 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -665,10 +665,18 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { - /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ - mask |= DW_VR_MII_AN_CTRL_8BIT; + switch (xpcs->sgmii_10_100_8bit) { + case DW_XPCS_SGMII_10_100_8BIT: val |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_4BIT: + mask |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_UNSET: + break; + } + + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { /* Hardware requires it to be PHY side SGMII */ tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; } else { @@ -1489,10 +1497,12 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { xpcs->pcs.poll = false; - else + xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT; + } else { xpcs->need_reset = true; + } return xpcs; diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 929fa238445e..268a9be21c77 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -105,6 +105,12 @@ enum dw_xpcs_clock { DW_XPCS_NUM_CLKS, }; +enum dw_xpcs_sgmii_10_100 { + DW_XPCS_SGMII_10_100_UNSET, + DW_XPCS_SGMII_10_100_4BIT, + DW_XPCS_SGMII_10_100_8BIT +}; + struct dw_xpcs { struct dw_xpcs_info info; const struct dw_xpcs_desc *desc; @@ -113,6 +119,8 @@ struct dw_xpcs { struct phylink_pcs pcs; phy_interface_t interface; bool need_reset; + /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ + enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit; u8 eee_mult_fact; }; -- 2.30.2