From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
Subject: [PATCH net-next 2/4] net: xpcs: document SGMII settings
Document some of the SGMII register settings.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/pcs/pcs-xpcs.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index ee0c1a27f06c..477a3a20f860 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -666,6 +666,7 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
DW_VR_MII_PCS_MODE_C37_SGMII);
if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
+ /* Width of the MII MAC/XPCS interface in 100M and 10M modes */
mask |= DW_VR_MII_AN_CTRL_8BIT;
val |= DW_VR_MII_AN_CTRL_8BIT;
/* Hardware requires it to be PHY side SGMII */
@@ -683,9 +684,18 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
val = 0;
mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ /* MAC_AUTO_SW only applies for MAC-side SGMII. */
if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ /* PHY_MODE_CTRL only applies for PHY-side SGMII. When PHY_MODE_CTRL
+ * is set, the SGMII tx_config register bits 15 (link), 12 (duplex)
+ * and 11:10 (speed) sent is derived from hardware inputs to the XPCS.
+ * When clear, bit 15 comes from DW_VR_MII_AN_CTRL bit 4, bit 12 from
+ * MII_ADVERTISE bit 5, and bits 11:10 from MII_BMCR speed bits. In
+ * the latter case, some implementation documentatoin states that
+ * MII_ADVERTISE must be written last.
+ */
if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
--
2.30.2