| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <3a501891-3181-40fc-b4a4-6340bfc9250a@alliedtelesis.co.nz>
Date: Fri, 31 Jan 2025 01:16:52 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: "lee@...nel.org" <lee@...nel.org>, "robh@...nel.org" <robh@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
<conor+dt@...nel.org>, "andrew+netdev@...n.ch" <andrew+netdev@...n.ch>,
"davem@...emloft.net" <davem@...emloft.net>, "edumazet@...gle.com"
<edumazet@...gle.com>, "kuba@...nel.org" <kuba@...nel.org>,
"pabeni@...hat.com" <pabeni@...hat.com>, "tsbogend@...ha.franken.de"
<tsbogend@...ha.franken.de>, "hkallweit1@...il.com" <hkallweit1@...il.com>,
"linux@...linux.org.uk" <linux@...linux.org.uk>, "sander@...nheule.net"
<sander@...nheule.net>, "markus.stockhausen@....de"
<markus.stockhausen@....de>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>
Subject: Re: [PATCH v5 4/4] net: mdio: Add RTL9300 MDIO driver
On 31/01/2025 14:01, Chris Packham wrote:
> Add a driver for the MDIO controller on the RTL9300 family of Ethernet
> switches with integrated SoC. There are 4 physical SMI interfaces on the
> RTL9300 however access is done using the switch ports. The driver takes
> the MDIO bus hierarchy from the DTS and uses this to configure the
> switch ports so they are associated with the correct PHY. This mapping
> is also used when dealing with software requests from phylib.
>
> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
> ---
>
> Notes:
> Changes in v5:
> - Reword out of date comment
> - Use GENMASK/FIELD_PREP where appropriate
> - Introduce port validity bitmap.
> - Use more obvious names for PHY_CTRL_READ/WRITE and
> PHY_CTRL_TYPE_C45/C22
> Changes in v4:
> - rename to realtek-rtl9300
> - s/realtek_/rtl9300_/
> - add locking to support concurrent access
> - The dtbinding now represents the MDIO bus hierarchy so we consume this
> information and use it to configure the switch port to MDIO bus+addr.
> Changes in v3:
> - Fix (another) off-by-one error
> Changes in v2:
> - Add clause 22 support
> - Remove commented out code
> - Formatting cleanup
> - Set MAX_PORTS correctly for MDIO interface
> - Fix off-by-one error in pn check
>
> drivers/net/mdio/Kconfig | 7 +
> drivers/net/mdio/Makefile | 1 +
> drivers/net/mdio/mdio-realtek-rtl9300.c | 436 ++++++++++++++++++++++++
> 3 files changed, 444 insertions(+)
> create mode 100644 drivers/net/mdio/mdio-realtek-rtl9300.c
>
> diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig
> index 4a7a303be2f7..058fcdaf6c18 100644
> --- a/drivers/net/mdio/Kconfig
> +++ b/drivers/net/mdio/Kconfig
> @@ -185,6 +185,13 @@ config MDIO_IPQ8064
> This driver supports the MDIO interface found in the network
> interface units of the IPQ8064 SoC
>
> +config MDIO_REALTEK_RTL9300
> + tristate "Realtek RTL9300 MDIO interface support"
> + depends on MACH_REALTEK_RTL || COMPILE_TEST
> + help
> + This driver supports the MDIO interface found in the Realtek
> + RTL9300 family of Ethernet switches with integrated SoC.
> +
> config MDIO_REGMAP
> tristate
> help
> diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile
> index 1015f0db4531..c23778e73890 100644
> --- a/drivers/net/mdio/Makefile
> +++ b/drivers/net/mdio/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
> obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
> obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o
> obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
> +obj-$(CONFIG_MDIO_REALTEK_RTL9300) += mdio-realtek-rtl9300.o
> obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o
> obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
> obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
> diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c
> new file mode 100644
> index 000000000000..d2ee66890caf
> --- /dev/null
> +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
> @@ -0,0 +1,436 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * MDIO controller for RTL9300 switches with integrated SoC.
> + *
> + * The MDIO communication is abstracted by the switch. At the software level
> + * communication uses the switch port to address the PHY. We work out the
> + * mapping based on the MDIO bus described in device tree and the realtek,port
> + * property.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bitmap.h>
> +#include <linux/bits.h>
> +#include <linux/cleanup.h>
> +#include <linux/find.h>
> +#include <linux/mdio.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/mutex.h>
> +#include <linux/of_mdio.h>
> +#include <linux/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +
> +#define SMI_GLB_CTRL 0xca00
> +#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf))
> +#define SMI_PORT0_15_POLLING_SEL 0xca08
> +#define SMI_POLL_CTRL 0xca90
> +#define SMI_ACCESS_PHY_CTRL_0 0xcb70
> +#define SMI_ACCESS_PHY_CTRL_1 0xcb74
> +#define PHY_CTRL_WRITE BIT(2)
> +#define PHY_CTRL_READ 0
> +#define PHY_CTRL_TYPE_C45 BIT(1)
> +#define PHY_CTRL_TYPE_C22 0
> +#define PHY_CTRL_CMD BIT(0)
> +#define PHY_CTRL_FAIL BIT(25)
> +#define SMI_ACCESS_PHY_CTRL_2 0xcb78
> +#define SMI_ACCESS_PHY_CTRL_3 0xcb7c
> +#define SMI_PORT0_5_ADDR_CTRL 0xcb80
> +
> +#define MAX_PORTS 28
> +#define MAX_SMI_BUSSES 4
> +#define MAX_SMI_ADDR 0x1f
> +
> +struct rtl9300_mdio_priv {
> + struct regmap *regmap;
> + struct mutex lock; /* protect HW access */
> + DECLARE_BITMAP(valid_ports, MAX_PORTS);
> + u8 smi_bus[MAX_PORTS];
> + u8 smi_addr[MAX_PORTS];
> + bool smi_bus_is_c45[MAX_SMI_BUSSES];
> + struct mii_bus *bus[MAX_SMI_BUSSES];
> +};
> +
> +struct rtl9300_mdio_chan {
> + struct rtl9300_mdio_priv *priv;
> + u8 mdio_bus;
> +};
> +
> +static int rtl9300_mdio_phy_to_port(struct mii_bus *bus, int phy_id)
> +{
> + struct rtl9300_mdio_chan *chan = bus->priv;
> + struct rtl9300_mdio_priv *priv = chan->priv;
> + int i;
> +
> + for (i = find_first_bit(priv->valid_ports, MAX_PORTS);
> + i < MAX_PORTS;
> + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1))
> + if (priv->smi_bus[i] == chan->mdio_bus &&
> + priv->smi_addr[i] == phy_id)
> + return i;
> +
> + return -ENOENT;
> +}
> +
> +static int rtl9300_mdio_wait_ready(struct rtl9300_mdio_priv *priv)
> +{
> + struct regmap *regmap = priv->regmap;
> + u32 val;
> +
> + lockdep_assert_held(&priv->lock);
> +
> + return regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
> + val, !(val & PHY_CTRL_CMD), 10, 1000);
> +}
> +
> +static int rtl9300_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
> +{
> + struct rtl9300_mdio_chan *chan = bus->priv;
> + struct rtl9300_mdio_priv *priv = chan->priv;
> + struct regmap *regmap = priv->regmap;
> + int port;
> + u32 val;
> + int err;
> +
> + guard(mutex)(&priv->lock);
> +
> + port = rtl9300_mdio_phy_to_port(bus, phy_id);
> + if (port < 0)
> + return port;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, port << 16);
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(24, 20), regnum) |
> + FIELD_PREP(GENMASK(19, 15), 0x1f) |
> + FIELD_PREP(GENMASK(14, 3), 0xfff) |
> + PHY_CTRL_READ | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
> + if (err)
> + return err;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val);
> + if (err)
> + return err;
> +
> + return FIELD_GET(GENMASK(15, 0), val);
> +}
> +
> +static int rtl9300_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value)
> +{
> + struct rtl9300_mdio_chan *chan = bus->priv;
> + struct rtl9300_mdio_priv *priv = chan->priv;
> + struct regmap *regmap = priv->regmap;
> + int port;
> + u32 val;
> + int err;
> +
> + guard(mutex)(&priv->lock);
> +
> + port = rtl9300_mdio_phy_to_port(bus, phy_id);
> + if (port < 0)
> + return port;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port));
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, value << 16);
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(24, 20), regnum) |
> + FIELD_PREP(GENMASK(19, 15), 0x1f) |
> + FIELD_PREP(GENMASK(14, 3), 0xfff) |
> + PHY_CTRL_WRITE | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
> + if (err)
> + return err;
> +
> + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
> + val, !(val & PHY_CTRL_CMD), 10, 100);
> + if (err)
> + return err;
> +
> + if (val & PHY_CTRL_FAIL)
> + return -ENXIO;
> +
> + return 0;
> +}
> +
> +static int rtl9300_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum)
> +{
> + struct rtl9300_mdio_chan *chan = bus->priv;
> + struct rtl9300_mdio_priv *priv = chan->priv;
> + struct regmap *regmap = priv->regmap;
> + int port;
> + u32 val;
> + int err;
> +
> + guard(mutex)(&priv->lock);
> +
> + port = rtl9300_mdio_phy_to_port(bus, phy_id);
> + if (port < 0)
> + return port;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(31, 16), port);
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val);
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(20, 16), dev_addr) |
> + FIELD_PREP(GENMASK(15, 0), regnum);
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val);
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
> + PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD);
> + if (err)
> + return err;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val);
> + if (err)
> + return err;
> +
> + return FIELD_GET(GENMASK(15, 0), val);
> +}
> +
> +static int rtl9300_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr,
> + int regnum, u16 value)
> +{
> + struct rtl9300_mdio_chan *chan = bus->priv;
> + struct rtl9300_mdio_priv *priv = chan->priv;
> + struct regmap *regmap = priv->regmap;
> + int port;
> + u32 val;
> + int err;
> +
> + guard(mutex)(&priv->lock);
> +
> + port = rtl9300_mdio_phy_to_port(bus, phy_id);
> + if (port < 0)
> + return port;
> +
> + err = rtl9300_mdio_wait_ready(priv);
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port));
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(31, 16), value);
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val);
> + if (err)
> + return err;
> +
> + val = FIELD_PREP(GENMASK(20, 16), dev_addr) |
> + FIELD_PREP(GENMASK(15, 0), regnum);
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val);
> + if (err)
> + return err;
> +
> + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
> + PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD);
> + if (err)
> + return err;
> +
> + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
> + val, !(val & PHY_CTRL_CMD), 10, 100);
> + if (err)
> + return err;
> +
> + if (val & PHY_CTRL_FAIL)
> + return -ENXIO;
> +
> + return 0;
> +}
> +
> +static int rtl9300_mdiobus_init(struct rtl9300_mdio_priv *priv)
> +{
> + u32 glb_ctrl_mask = 0, glb_ctrl_val = 0;
> + struct regmap *regmap = priv->regmap;
> + u32 port_addr[5] = { 0 };
> + u32 poll_sel[2] = { 0 };
> + int i, err;
> +
> + /* Associate the port with the SMI interface and PHY */
> + for (i = find_first_bit(priv->valid_ports, MAX_PORTS);
> + i < MAX_PORTS;
> + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1)) {
> + int pos;
> +
> + pos = (i % 6) * 5;
> + port_addr[i / 6] |= (priv->smi_addr[i] & 0x1f) << pos;
> +
> + pos = (i % 16) * 2;
> + poll_sel[i / 16] |= (priv->smi_bus[i] & 0x3) << pos;
> + }
> +
> + /* Stop the PPU from interfering */
> + err = regmap_update_bits(regmap, SMI_POLL_CTRL, priv->valid_ports, 0);
> + if (err)
> + return err;
drivers/net/mdio/mdio-realtek-rtl9300.c:295:61: warning: passing
argument 3 of 'regmap_update_bits' makes integer from pointer without a
cast [-Wint-conversion]
295 | err = regmap_update_bits(regmap, SMI_POLL_CTRL,
priv->valid_ports, 0);
| ~~~~^~~~~~~~~~~~~
| |
| long unsigned int *
darn not sure how I missed that.
> +
> + /* Put the interfaces into C45 mode if required */
> + glb_ctrl_mask = GENMASK(19, 16);
> + for (i = 0; i < MAX_SMI_BUSSES; i++)
> + if (priv->smi_bus_is_c45[i])
> + glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
> +
> + err = regmap_bulk_write(regmap, SMI_PORT0_5_ADDR_CTRL,
> + port_addr, 5);
> + if (err)
> + return err;
> +
> + err = regmap_bulk_write(regmap, SMI_PORT0_15_POLLING_SEL,
> + poll_sel, 2);
> + if (err)
> + return err;
> +
> + err = regmap_update_bits(regmap, SMI_GLB_CTRL,
> + glb_ctrl_mask, glb_ctrl_val);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static int rtl9300_mdiobus_probe_one(struct device *dev, struct rtl9300_mdio_priv *priv,
> + struct fwnode_handle *node)
> +{
> + struct rtl9300_mdio_chan *chan;
> + struct fwnode_handle *child;
> + struct mii_bus *bus;
> + u32 mdio_bus;
> + int err;
> +
> + err = fwnode_property_read_u32(node, "reg", &mdio_bus);
> + if (err)
> + return err;
> +
> + if (mdio_bus >= MAX_SMI_BUSSES)
> + return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", mdio_bus);
> +
> + fwnode_for_each_child_node(node, child) {
> + u32 addr;
> + u32 pn;
> +
> + err = fwnode_property_read_u32(child, "reg", &addr);
> + if (err)
> + return err;
> +
> + err = fwnode_property_read_u32(child, "realtek,port", &pn);
> + if (err)
> + return err;
> +
> + if (pn >= MAX_PORTS)
> + return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn);
> +
> + if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45"))
> + priv->smi_bus_is_c45[mdio_bus] = true;
> +
> + bitmap_set(priv->valid_ports, pn, 1);
> + priv->smi_bus[pn] = mdio_bus;
> + priv->smi_addr[pn] = addr;
> + }
> +
> + bus = devm_mdiobus_alloc_size(dev, sizeof(*chan));
> + if (!bus)
> + return -ENOMEM;
> +
> + bus->name = "Reaktek Switch MDIO Bus";
> + bus->read = rtl9300_mdio_read_c22;
> + bus->write = rtl9300_mdio_write_c22;
> + bus->read_c45 = rtl9300_mdio_read_c45;
> + bus->write_c45 = rtl9300_mdio_write_c45;
> + bus->parent = dev;
> + chan = bus->priv;
> + chan->mdio_bus = mdio_bus;
> + chan->priv = priv;
> +
> + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus);
> +
> + err = devm_of_mdiobus_register(dev, bus, to_of_node(node));
> + if (err)
> + return dev_err_probe(dev, err, "cannot register MDIO bus\n");
> +
> + return 0;
> +}
> +
> +static int rtl9300_mdiobus_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rtl9300_mdio_priv *priv;
> + struct fwnode_handle *child;
> + int err;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + err = devm_mutex_init(dev, &priv->lock);
> + if (err)
> + return err;
> +
> + priv->regmap = syscon_node_to_regmap(dev->parent->of_node);
> + if (IS_ERR(priv->regmap))
> + return PTR_ERR(priv->regmap);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + device_for_each_child_node(dev, child) {
> + err = rtl9300_mdiobus_probe_one(dev, priv, child);
> + if (err)
> + return err;
> + }
> +
> + err = rtl9300_mdiobus_init(priv);
> + if (err)
> + return dev_err_probe(dev, err, "failed to initialise MDIO bus controller\n");
> +
> + return 0;
> +}
> +
> +static const struct of_device_id rtl9300_mdio_ids[] = {
> + { .compatible = "realtek,rtl9301-mdio" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, rtl9300_mdio_ids);
> +
> +static struct platform_driver rtl9300_mdio_driver = {
> + .probe = rtl9300_mdiobus_probe,
> + .driver = {
> + .name = "mdio-rtl9300",
> + .of_match_table = rtl9300_mdio_ids,
> + },
> +};
> +
> +module_platform_driver(rtl9300_mdio_driver);
> +
> +MODULE_DESCRIPTION("RTL9300 MDIO driver");
> +MODULE_LICENSE("GPL");
Powered by blists - more mailing lists