[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id: <20250207180254.549314-4-arkadiusz.kubalewski@intel.com>
Date: Fri, 7 Feb 2025 19:02:54 +0100
From: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
To: intel-wired-lan@...ts.osuosl.org
Cc: netdev@...r.kernel.org,
Karol Kolacinski <karol.kolacinski@...el.com>,
Milena Olech <milena.olech@...el.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
Subject: [PATCH iwl-next 3/3] ice: add ice driver PTP pin documentation
From: Karol Kolacinski <karol.kolacinski@...el.com>
Add a description of PTP pins support by the adapters to ice driver
documentation.
Reviewed-by: Milena Olech <milena.olech@...el.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>
---
.../device_drivers/ethernet/intel/ice.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/networking/device_drivers/ethernet/intel/ice.rst b/Documentation/networking/device_drivers/ethernet/intel/ice.rst
index 3c46a48d99ba..0bca293cf9cb 100644
--- a/Documentation/networking/device_drivers/ethernet/intel/ice.rst
+++ b/Documentation/networking/device_drivers/ethernet/intel/ice.rst
@@ -927,6 +927,19 @@ To enable/disable UDP Segmentation Offload, issue the following command::
# ethtool -K <ethX> tx-udp-segmentation [off|on]
+PTP pin interface
+-----------------
+All adapters support standard PTP pin interface. SDPs (Software Definable Pin)
+are single ended pins with both periodic output and external timestamp
+supported. There are also specific differential input/output pins (TIME_SYNC,
+1PPS) with only one of the functions supported.
+
+There are adapters with DPLL, where pins are connected to the DPLL instead of
+being exposed on the board. You have to be aware that in those configurations,
+only SDP pins are exposed and each pin has its own fixed direction.
+To see input signal on those PTP pins, you need to configure DPLL properly.
+Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins,
+DPLL output pins have to be manually configured.
GNSS module
-----------
--
2.38.1
Powered by blists - more mailing lists