netdev - RE: [PATCH RFC net-next 2/4] net: xpcs: add SGMII mode setting

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Message-ID:
 <DM3PR11MB873689D00EDF038BE43F0351ECF12@DM3PR11MB8736.namprd11.prod.outlook.com>
Date: Fri, 7 Feb 2025 18:46:24 +0000
From: <Tristram.Ha@...rochip.com>
To: <rmk+kernel@...linux.org.uk>
CC: <olteanv@...il.com>, <UNGLinuxDriver@...rochip.com>,
	<Woojung.Huh@...rochip.com>, <andrew@...n.ch>, <hkallweit1@...il.com>,
	<davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
	<pabeni@...hat.com>, <netdev@...r.kernel.org>
Subject: RE: [PATCH RFC net-next 2/4] net: xpcs: add SGMII mode setting

> -----Original Message-----
> From: Russell King <rmk@...linux.org.uk> On Behalf Of Russell King (Oracle)
> Sent: Wednesday, February 5, 2025 5:28 AM
> To: Tristram Ha - C24268 <Tristram.Ha@...rochip.com>
> Cc: Vladimir Oltean <olteanv@...il.com>; UNGLinuxDriver
> <UNGLinuxDriver@...rochip.com>; Woojung Huh - C21699
> <Woojung.Huh@...rochip.com>; Andrew Lunn <andrew@...n.ch>; Heiner Kallweit
> <hkallweit1@...il.com>; David S. Miller <davem@...emloft.net>; Eric Dumazet
> <edumazet@...gle.com>; Jakub Kicinski <kuba@...nel.org>; Paolo Abeni
> <pabeni@...hat.com>; netdev@...r.kernel.org
> Subject: [PATCH RFC net-next 2/4] net: xpcs: add SGMII mode setting
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content
> is safe
> 
> Add SGMII mode setting which configures whether XPCS immitates the MAC
> end of the link or the PHY end, and in the latter case, where the data
> for generating the link's configuration word comes from. This ties up
> all the register bits necessary to configure this mode into one
> control.
> 
> Set this to PHY_HW mode for TXGBE.
> 
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
> ---
>  drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++--------
>  drivers/net/pcs/pcs-xpcs.h | 14 ++++++++++++++
>  2 files changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
> index 12a3d5a80b45..9d54c04ef6ee 100644
> --- a/drivers/net/pcs/pcs-xpcs.c
> +++ b/drivers/net/pcs/pcs-xpcs.c
> @@ -706,12 +706,10 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs
> *xpcs,
>                 break;
>         }
> 
> -       if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
> -               /* Hardware requires it to be PHY side SGMII */
> -               tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
> -       } else {
> +       if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC)
>                 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
> -       }
> +       else
> +               tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
> 
>         val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf);
> 
> @@ -722,12 +720,16 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs
> *xpcs,
>         val = 0;
>         mask = DW_VR_MII_DIG_CTRL1_2G5_EN |
> DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
> 
> -       if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> -               val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
> +       switch (xpcs->sgmii_mode) {
> +       case DW_XPCS_SGMII_MODE_MAC:
> +               if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> +                       val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
> +               break;
> 
> -       if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
> +       case DW_XPCS_SGMII_MODE_PHY_HW:
>                 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
>                 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
> +               break;
>         }
> 
>         ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask,
> val);
> @@ -1462,6 +1464,7 @@ static struct dw_xpcs *xpcs_create(struct mdio_device
> *mdiodev)
>         if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
>                 xpcs->pcs.poll = false;
>                 xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT;
> +               xpcs->sgmii_mode = DW_XPCS_SGMII_MODE_PHY_HW;
>         } else {
>                 xpcs->need_reset = true;
>         }
> diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h
> index 4d53ccf917f3..892b85425787 100644
> --- a/drivers/net/pcs/pcs-xpcs.h
> +++ b/drivers/net/pcs/pcs-xpcs.h
> @@ -120,6 +120,19 @@ enum dw_xpcs_sgmii_10_100 {
>         DW_XPCS_SGMII_10_100_8BIT
>  };
> 
> +/* The SGMII mode:
> + * DW_XPCS_SGMII_MODE_MAC: the XPCS acts as a MAC, reading and
> acknowledging
> + * the config word.
> + *
> + * DW_XPCS_SGMII_MODE_PHY_HW: the XPCS acts as a PHY, deriving the tx_config
> + * bits 15 (link), 12 (duplex) and 11:10 (speed) from hardware inputs to the
> + * XPCS.
> + */
> +enum dw_xpcs_sgmii_mode {
> +       DW_XPCS_SGMII_MODE_MAC,         /* XPCS is MAC on SGMII */
> +       DW_XPCS_SGMII_MODE_PHY_HW,      /* XPCS is PHY, tx_config from hw */
> +};
> +
>  struct dw_xpcs {
>         struct dw_xpcs_info info;
>         const struct dw_xpcs_desc *desc;
> @@ -130,6 +143,7 @@ struct dw_xpcs {
>         bool need_reset;
>         /* Width of the MII MAC/XPCS interface in 100M and 10M modes */
>         enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit;
> +       enum dw_xpcs_sgmii_mode sgmii_mode;
>  };
> 
>  int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
> --

Tested-by: Tristram Ha <tristram.ha@...rochip.com>