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Message-ID: <d95286ee-e929-4fd2-bfca-932368ae5391@foss.st.com>
Date: Fri, 14 Feb 2025 15:12:52 +0100
From: Amelie Delaunay <amelie.delaunay@...s.st.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Richard Cochran <richardcochran@...il.com>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<netdev@...r.kernel.org>
Subject: Re: [PATCH 04/10] arm64: dts: st: introduce stm32mp23 SoCs family
On 2/13/25 10:08, Krzysztof Kozlowski wrote:
> On Mon, Feb 10, 2025 at 04:20:58PM +0100, Amelie Delaunay wrote:
>> From: Alexandre Torgue <alexandre.torgue@...s.st.com>
>>
>> STM32MP23 family is composed of 3 SoCs defined as following:
>>
>> -STM32MP231: common part composed of 1*Cortex-A35, common peripherals
>> like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ...
>>
>> -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD.
>>
>> -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS
>> display.
>>
>> A second diversity layer exists for security features/ A35 frequency:
>> -STM32MP23xY, "Y" gives information:
>> -Y = A means A35@...GHz + no cryp IP and no secure boot.
>> -Y = C means A35@...GHz + cryp IP and secure boot.
>> -Y = D means A35@...GHz + no cryp IP and no secure boot.
>> -Y = F means A35@...GHz + cryp IP and secure boot.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
>> Signed-off-by: Amelie Delaunay <amelie.delaunay@...s.st.com>
>> ---
>> arch/arm64/boot/dts/st/stm32mp231.dtsi | 1216 +++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 +++
>> arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 +
>> arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 +
>> arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 +
>> 5 files changed, 1342 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..ee93f5412096a7cd30b228b85a5280a551fbfaf4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
>> @@ -0,0 +1,1216 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
>> + * Author: Alexandre Torgue <alexandre.torgue@...s.st.com> for STMicroelectronics.
>> + */
>> +#include <dt-bindings/clock/st,stm32mp25-rcc.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
>> +#include <dt-bindings/reset/st,stm32mp25-rcc.h>
>> +
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a35";
>> + device_type = "cpu";
>> + reg = <0>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + };
>> + };
>> +
>> + arm-pmu {
>> + compatible = "arm,cortex-a35-pmu";
>> + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu0>;
>> + interrupt-parent = <&intc>;
>> + };
>> +
>> + arm_wdt: watchdog {
>> + compatible = "arm,smc-wdt";
>> + arm,smc-id = <0xb200005a>;
>> + status = "disabled";
>> + };
>> +
>> + clocks {
>
> Drop
>
>> + clk_dsi_txbyte: txbyteclk {
>
> Use consistent naming style. Either prefix or suffix. Or better, use
> what is recommended.
>
> See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
>
Will use the recommended style:
clk_dsi_txbyte: clock-0
clk_rcbsec: clock-64000000
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <0>;
>> + };
>> +
>> + clk_rcbsec: clk-rcbsec {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <64000000>;
>> + };
>> + };
>> +
>> + firmware {
>> + optee: optee {
>> + compatible = "linaro,optee-tz";
>> + method = "smc";
>> + interrupt-parent = <&intc>;
>> + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +
>> + scmi {
>> + compatible = "linaro,scmi-optee";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + linaro,optee-channel-id = <0>;
>> +
>> + scmi_clk: protocol@14 {
>> + reg = <0x14>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + scmi_reset: protocol@16 {
>> + reg = <0x16>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + scmi_voltd: protocol@17 {
>> + reg = <0x17>;
>> +
>> + scmi_regu: regulators {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + scmi_vddio1: regulator@0 {
>> + reg = <VOLTD_SCMI_VDDIO1>;
>> + regulator-name = "vddio1";
>> + };
>> + scmi_vddio2: regulator@1 {
>> + reg = <VOLTD_SCMI_VDDIO2>;
>> + regulator-name = "vddio2";
>> + };
>> + scmi_vddio3: regulator@2 {
>> + reg = <VOLTD_SCMI_VDDIO3>;
>> + regulator-name = "vddio3";
>> + };
>> + scmi_vddio4: regulator@3 {
>> + reg = <VOLTD_SCMI_VDDIO4>;
>> + regulator-name = "vddio4";
>> + };
>> + scmi_vdd33ucpd: regulator@5 {
>> + reg = <VOLTD_SCMI_UCPD>;
>> + regulator-name = "vdd33ucpd";
>> + };
>> + scmi_vdda18adc: regulator@7 {
>> + reg = <VOLTD_SCMI_ADC>;
>> + regulator-name = "vdda18adc";
>> + };
>> + };
>> + };
>> + };
>> + };
>> +
>> + intc: interrupt-controller@...00000 {
>
> Part of Soc most likely.
>
Right.
>> + compatible = "arm,cortex-a7-gic";
>> + #interrupt-cells = <3>;
>> + #address-cells = <1>;
>> + interrupt-controller;
>> + reg = <0x0 0x4ac10000 0x0 0x1000>,
>> + <0x0 0x4ac20000 0x0 0x2000>,
>> + <0x0 0x4ac40000 0x0 0x2000>,
>> + <0x0 0x4ac60000 0x0 0x2000>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> +
>> + CPU_PD0: power-domain-cpu0 {
>
> All labels are always lowercase.
>
Sure. Wrongly inspired by the examples of
https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/psci.yaml
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + };
>> +
>> + CLUSTER_PD: power-domain-cluster {
>> + #power-domain-cells = <0>;
>> + power-domains = <&RET_PD>;
>> + };
>> +
>> + RET_PD: power-domain-retention {
>> + #power-domain-cells = <0>;
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupt-parent = <&intc>;
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
>> + always-on;
>> + };
>> +
>> + soc@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&intc>;
>> + ranges = <0x0 0x0 0x0 0x80000000>;
>
> Same comments as for all other patches.
>
Ok.
>> +
>> + hpdma: dma-controller@...00000 {
>> + compatible = "st,stm32mp25-dma3";
>> + reg = <0x40400000 0x1000>;
>> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&scmi_clk CK_SCMI_HPDMA1>;
>> + #dma-cells = <3>;
>> + };
>> +
>> + hpdma2: dma-controller@...10000 {
>> + compatible = "st,stm32mp25-dma3";
>> + reg = <0x40410000 0x1000>;
>> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&scmi_clk CK_SCMI_HPDMA2>;
>> + #dma-cells = <3>;
>> + };
>> +
>> + hpdma3: dma-controller@...20000 {
>> + compatible = "st,stm32mp25-dma3";
>> + reg = <0x40420000 0x1000>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&scmi_clk CK_SCMI_HPDMA3>;
>> + #dma-cells = <3>;
>> + };
>> +
>> + rifsc: bus@...80000 {
>> + compatible = "st,stm32mp25-rifsc", "simple-bus";
>> + reg = <0x42080000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #access-controller-cells = <1>;
>> + ranges;
>> +
>> + i2s2: audio-controller@...b0000 {
>
> Confusing: device has address outside of the bus. What does the bus
> address represent?
>
RIFSC is a Resource Isolation Framework Security Controller, aka a
firewall, on STM32 platforms. It manages isolation of STM32 hardware
resources like memory and peripherals.
The bus adresses of rifsc child nodes represent the address of the
peripherals on the AHB bus, while the access-controllers propriety
refers to RIFSC firewall ID.
Firewall is already used in
- arch/arm/boot/dts/st/stm32mp131.dtsi
- arch/arm/boot/dts/st/stm32mp151.dtsi
- arch/arm64/boot/dts/st/stm32mp251.dtsi
This was discussed here:
https://lore.kernel.org/linux-arm-kernel/20240105130404.301172-1-gatien.chevallier@foss.st.com/T/
>> + compatible = "st,stm32mp25-i2s";
>> + reg = <0x400b0000 0x400>;
>> + #sound-dai-cells = <0>;
>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
>> + clock-names = "pclk", "i2sclk";
>> + resets = <&rcc SPI2_R>;
>> + dmas = <&hpdma 51 0x43 0x12>,
>> + <&hpdma 52 0x43 0x21>;
>> + dma-names = "rx", "tx";
>> + access-controllers = <&rifsc 23>;
>> + status = "disabled";
>> + };
>> +
>
> ...
>
>> + sdmmc1: mmc@...20000 {
>> + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
>> + arm,primecell-periphid = <0x00353180>;
>> + reg = <0x48220000 0x400>, <0x44230400 0x8>;
>> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&rcc CK_KER_SDMMC1 >;
>> + clock-names = "apb_pclk";
>> + resets = <&rcc SDMMC1_R>;
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + max-frequency = <120000000>;
>> + access-controllers = <&rifsc 76>;
>> + status = "disabled";
>> + };
>> +
>> + ethernet1: ethernet@...c0000 {
>> + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
>> + reg = <0x482c0000 0x4000>;
>> + reg-names = "stmmaceth";
>> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>
> Why extended?
>
ethernet could be a wakeup source, but for that, it requires using an
interrupt from EXTI controller, not GIC. The use of interrupts-extended
property is a bit too advanced here, should be interrupts, unless all
wakeup stuff is added.
>> + interrupt-names = "macirq";
>> + clock-names = "stmmaceth",
>> + "mac-clk-tx",
>> + "mac-clk-rx",
>> + "ptp_ref",
>> + "ethstp",
>> + "eth-ck";
>
> ...
>
>> + rcc: clock-controller@...00000 {
>> + compatible = "st,stm32mp25-rcc";
>> + reg = <0x44200000 0x10000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + clocks = <&scmi_clk CK_SCMI_HSE>,
>> + <&scmi_clk CK_SCMI_HSI>,
>> + <&scmi_clk CK_SCMI_MSI>,
>> + <&scmi_clk CK_SCMI_LSE>,
>> + <&scmi_clk CK_SCMI_LSI>,
>> + <&scmi_clk CK_SCMI_HSE_DIV2>,
>> + <&scmi_clk CK_SCMI_ICN_HS_MCU>,
>> + <&scmi_clk CK_SCMI_ICN_LS_MCU>,
>> + <&scmi_clk CK_SCMI_ICN_SDMMC>,
>> + <&scmi_clk CK_SCMI_ICN_DDR>,
>> + <&scmi_clk CK_SCMI_ICN_DISPLAY>,
>> + <&scmi_clk CK_SCMI_ICN_HSL>,
>> + <&scmi_clk CK_SCMI_ICN_NIC>,
>> + <&scmi_clk CK_SCMI_ICN_VID>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_07>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_08>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_09>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_10>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_11>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_12>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_13>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_14>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_15>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_16>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_17>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_18>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_19>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_20>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_21>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_22>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_23>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_24>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_25>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_26>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_27>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_28>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_29>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_30>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_31>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_32>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_33>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_34>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_35>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_36>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_37>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_38>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_39>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_40>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_41>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_42>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_43>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_44>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_45>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_46>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_47>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_48>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_49>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_50>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_51>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_52>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_53>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_54>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_55>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_56>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_57>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_58>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_59>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_60>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_61>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_62>,
>> + <&scmi_clk CK_SCMI_FLEXGEN_63>,
>> + <&scmi_clk CK_SCMI_ICN_APB1>,
>> + <&scmi_clk CK_SCMI_ICN_APB2>,
>> + <&scmi_clk CK_SCMI_ICN_APB3>,
>> + <&scmi_clk CK_SCMI_ICN_APB4>,
>> + <&scmi_clk CK_SCMI_ICN_APBDBG>,
>> + <&scmi_clk CK_SCMI_TIMG1>,
>> + <&scmi_clk CK_SCMI_TIMG2>,
>> + <&scmi_clk CK_SCMI_PLL3>,
>> + <&clk_dsi_txbyte>;
>> + access-controllers = <&rifsc 156>;
>> + };
>> +
>> + exti1: interrupt-controller@...20000 {
>> + compatible = "st,stm32mp1-exti", "syscon";
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + reg = <0x44220000 0x400>;
>> + interrupts-extended =
>
> Why extended?
>
EXTI is an interrupt dispatcher that routes each client interrupt either
to GIC or to a wakeup-parent interrupt controller (not upstream yet).
The mapping between EXTI interrupts and parents interrupts is not linear
and has holes; together with the incoming need to address multi-parents,
all this matches with the use of interrupts-extended.
It is already used in
- arch/arm/boot/dts/st/stm32mp131.dtsi
- arch/arm/boot/dts/st/stm32mp151.dtsi
- arch/arm64/boot/dts/st/stm32mp251.dtsi
and reported in example 2 of the EXTI bindings.
https://lore.kernel.org/all/20240415134926.1254428-3-antonio.borneo@foss.st.com/
>> + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
>> + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
>> + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>, /* EXTI_20 */
>> + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
>> + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>,
>> + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */
>> + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>, /* EXTI_60 */
>> + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>,
>> + <0>,
>> + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>,
>> + <0>,
>> + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>,
>> + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
>> + <0>,
>> + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
>> + <0>, /* EXTI_80 */
>> + <0>,
>> + <0>,
>> + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + syscfg: syscon@...30000 {
>> + compatible = "st,stm32mp25-syscfg", "syscon";
>> + reg = <0x44230000 0x10000>;
>> + };
>> +
>> + pinctrl: pinctrl@...40000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> Please fix coding style everywhere here.
>
>
Ok.
>> + compatible = "st,stm32mp257-pinctrl";
>> + ranges = <0 0x44240000 0xa0400>;
>> + interrupt-parent = <&exti1>;
>> + st,syscfg = <&exti1 0x60 0xff>;
>> + pins-are-numbered;
>> +
>
> ...
>
>> diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..e33b00b424e1207dc6212e75235785f8c61e5055
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi
>> @@ -0,0 +1,8 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
>> + * Author: Alexandre Torgue <alexandre.torgue@...s.st.com> for STMicroelectronics.
>> + */
>> +
>
> What is the point of this file?
>
stm32mp23xc.dtsi and stm32mp23xf.dtsi are skeleton files pending
cryptographic support.
Same split is used on other STM32 MPUs:
./arch/arm/boot/dts/st/stm32mp13xc.dtsi
./arch/arm/boot/dts/st/stm32mp13xf.dtsi
./arch/arm/boot/dts/st/stm32mp15xc.dtsi
./arch/arm/boot/dts/st/stm32mp15xf.dtsi
./arch/arm64/boot/dts/st/stm32mp25xc.dtsi
./arch/arm64/boot/dts/st/stm32mp25xf.dtsi
Regards,
Amelie
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