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Message-Id: <20250221123123.2833395-1-grzegorz.nitka@intel.com>
Date: Fri, 21 Feb 2025 13:31:20 +0100
From: Grzegorz Nitka <grzegorz.nitka@...el.com>
To: intel-wired-lan@...ts.osuosl.org
Cc: netdev@...r.kernel.org,
Grzegorz Nitka <grzegorz.nitka@...el.com>
Subject: [PATCH iwl-next v1 0/3] E825C timesync dual NAC support
This patch series adds full support for timesync operations for E8225C
devices which are configured in so called 2xNAC mode (Network
Acceleration Complex). 2xNAC mode is the mode in which IO die
is housing two complexes and each of them has its own PHY connected
to it. The complex which controls time transmitter is referred as
primary complex.
The series solves known configuration issues in dual config mode:
- side-band queue (SBQ) addressing when configuring the ports on the PHY
on secondary NAC
- access to timesync config from the second NAC as only one PF in
primary NAC controls time transmitter clock
Karol Kolacinski (3):
ice: remove SW side band access workaround for E825
ice: refactor ice_sbq_msg_dev enum
ice: enable timesync operation on 2xNAC E825 devices
drivers/net/ethernet/intel/ice/ice.h | 60 +++++++++++++-
drivers/net/ethernet/intel/ice/ice_common.c | 8 +-
drivers/net/ethernet/intel/ice/ice_ptp.c | 49 +++++++++---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 82 ++++++++++----------
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 5 --
drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 11 +--
drivers/net/ethernet/intel/ice/ice_type.h | 1 +
7 files changed, 149 insertions(+), 67 deletions(-)
base-commit: 692375ca2a4e6916ddc2ef0d73faa37c7a93cd1a
--
2.39.3
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