netdev - Re: [PATCH net-next 3/3] r8169: disable RTL8126 ZRX-DC timeout

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Message-ID: <20250221203511.GA359929@bhelgaas>
Date: Fri, 21 Feb 2025 14:35:11 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Heiner Kallweit <hkallweit1@...il.com>
Cc: ChunHao Lin <hau@...ltek.com>, nic_swsd@...ltek.com,
	andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, pabeni@...hat.com, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 3/3] r8169: disable RTL8126 ZRX-DC timeout

On Fri, Feb 21, 2025 at 09:12:09PM +0100, Heiner Kallweit wrote:
> On 21.02.2025 21:01, Bjorn Helgaas wrote:
> > On Fri, Feb 21, 2025 at 03:18:28PM +0800, ChunHao Lin wrote:
> >> Disable it due to it dose not meet ZRX-DC specification. If it is enabled,
> >> device will exit L1 substate every 100ms. Disable it for saving more power
> >> in L1 substate.
> > 
> > s/dose/does/
> > 
> > Is ZRX-DC a PCIe spec?  A Google search suggests that it might not be
> > completely Realtek-specific?
> > 
> ZRX-DC is the receiver DC impedance as specified in the PCIe Base
> Specification.  From what I've found after a quick search ASPM
> restrictions apply if this impedance isn't in the range 40-60 ohm.

Ah, so it looks like PCIe r6.0, sec 4.2.7.6.1.2, is the sort of thing
this refers to:

  4.2.7.6.1.2 Rx_L0s.Idle §

    - Next state is Rx_L0s.FTS if the Receiver detects an exit from
      Electrical Idle on any Lane of the configured Link.

    - Next state is Rx_L0s.FTS after a 100 ms timeout if the current
      data rate is 8.0 GT/s or higher and the Port’s Receivers do not
      meet the ZRX-DC specification for 2.5 GT/s (see § Table 8-11).
      All Ports are permitted to implement the timeout and transition
      to Rx_L0s.FTS when the data rate is 8.0 GT/s or higher.

> >> +static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
> >> +{
> >> +	struct pci_dev *pdev = tp->pci_dev;
> >> +	u8 val;
> >> +
> >> +	if (pdev->cfg_size > 0x0890 &&
> >> +	    pci_read_config_byte(pdev, 0x0890, &val) == PCIBIOS_SUCCESSFUL &&
> >> +	    pci_write_config_byte(pdev, 0x0890, val & ~BIT(0)) == PCIBIOS_SUCCESSFUL)
> > 
> > Is this a standard PCIe extended capability?  If so, it would be nice
> > to search for it with pci_find_ext_capability() and use standard
> > #defines.

I guess we could tell from "sudo lspci -vv" output whether this is a
standard capability.

Bjorn