netdev - Re: [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: remove SW side band access workaround for E825

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Message-ID: <aecd919b-fbb8-4790-af1f-69b50cc78438@molgen.mpg.de>
Date: Fri, 21 Feb 2025 22:16:09 +0100
From: Paul Menzel <pmenzel@...gen.mpg.de>
To: Grzegorz Nitka <grzegorz.nitka@...el.com>,
 Karol Kolacinski <karol.kolacinski@...el.com>
Cc: intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org,
 Przemek Kitszel <przemyslaw.kitszel@...el.com>,
 Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: remove SW side
 band access workaround for E825

Dear Grzegorz, dear Karol,


Thank you for your patch.

Am 21.02.25 um 13:31 schrieb Grzegorz Nitka:
> From: Karol Kolacinski <karol.kolacinski@...el.com>
> 
> Due to the bug in FW/NVM autoload mechanism (wrong default
> SB_REM_DEV_CTL register settings), the access to peer PHY and CGU
> clients was disabled by default.

I’d add a blank line between the paragraphs.

> As the workaround solution, the register value was overwritten by the
> driver at the probe or reset handling.
> Remove workaround as it's not needed anymore. The fix in autoload
> procedure has been provided with NVM 3.80 version.

Is this compatible with Linux’ no regression policy? People might only 
update the Linux kernel and not the firmware.

How did you test this, and how can others test this?

> Reviewed-by: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> ---
>   drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 ---------------------
>   1 file changed, 23 deletions(-)


Kind regards,

Paul


> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index 89bb8461284a..a5df081ffc19 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -2630,25 +2630,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
>   	return 0;
>   }
>   
> -/**
> - * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
> - * @hw: pointer to HW struct
> - * @enable: Enable or disable access
> - *
> - * Enable sideband devices (PHY and others) access.
> - */
> -static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
> -{
> -	u32 val = rd32(hw, PF_SB_REM_DEV_CTL);
> -
> -	if (enable)
> -		val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);
> -	else
> -		val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));
> -
> -	wr32(hw, PF_SB_REM_DEV_CTL, val);
> -}
> -
>   /**
>    * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
>    * @hw: pointer to HW struct
> @@ -2659,8 +2640,6 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
>    */
>   static int ice_ptp_init_phc_e825(struct ice_hw *hw)
>   {
> -	ice_sb_access_ena_eth56g(hw, true);
> -
>   	/* Initialize the Clock Generation Unit */
>   	return ice_init_cgu_e82x(hw);
>   }
> @@ -2747,8 +2726,6 @@ static void ice_ptp_init_phy_e825(struct ice_hw *hw)
>   	params->num_phys = 2;
>   	ptp->ports_per_phy = 4;
>   	ptp->num_lports = params->num_phys * ptp->ports_per_phy;
> -
> -	ice_sb_access_ena_eth56g(hw, true);
>   }
>   
>   /* E822 family functions