From: "Russell King (Oracle)" Bcc: linux@mail.armlinux.org.uk Subject: [PATCH net-next 5/5] net: stmmac: call phylink_prepare_resume() MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" The stmmac core needs the receive clock to be running in order to complete its software triggered reset. However, the media link may be in EEE low-power mode, and as the driver allows the PHY receive clock to be disabled, the receive clock may not be present while resuming. This has been observed with Tegra 186. Fix this by using the newly provided phylink_prepare_resume() to temporarily disable receive clock stop while resuming. phylink_resume() will restore the receive clock stop setting according to the configuration passed from the netdev driver. Signed-off-by: Russell King (Oracle) --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 262718e5c4f3..31ec1818211d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -7925,6 +7925,8 @@ int stmmac_resume(struct device *dev) } rtnl_lock(); + phylink_prepare_resume(priv->phylink); + mutex_lock(&priv->lock); stmmac_reset_queues_param(priv); -- 2.30.2