netdev - Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas RZ/V2H(P) SoC

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Message-ID: <CA+V-a8sCMn+v5y5v9CyyV2VsRmLj-Uyowt61tTS9dWN43CD0_A@mail.gmail.com>
Date: Sun, 2 Mar 2025 20:41:39 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Andrew Lunn <andrew@...n.ch>, Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, 
	"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>, Giuseppe Cavallaro <peppe.cavallaro@...com>, 
	Jose Abreu <joabreu@...opsys.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, 
	netdev@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas
 RZ/V2H(P) SoC

Hi Andrew,

On Sun, Mar 2, 2025 at 7:25 PM Andrew Lunn <andrew@...n.ch> wrote:
>
> > +  clock-names:
> > +    items:
> > +      - const: stmmaceth
> > +      - const: pclk
> > +      - const: ptp_ref
> > +      - const: tx
> > +      - const: rx
> > +      - const: tx-180
> > +      - const: rx-180
>
> As Russell said in an older thread, tx and tx-180 are effectively the
> same clock, but with an inverter added. You should be able to arrange
> the clock tree that if you enable tx, it also enables tx-180 as a
> parent/sibling relationship.
>
I can certainly do that, but not sure in the DT we will be describing
the HW correctly then. I'll have to hide *-180  clocks In the DT and
handle and turning on/off these clocks in the clock driver.

Currently
eth0: ethernet@...30000 {
             compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
                               "snps,dwmac-5.20";
             reg = <0 0x15c30000 0 0x10000>;
             interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
                                         "tx0", "tx1", "tx2", "tx3",
                                         "rx0", "rx1", "rx2", "rx3";
             clocks =  <&cpg CPG_MOD 0xbd>,
                            <&cpg CPG_MOD 0xbc>,
                            <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
                            <&cpg CPG_MOD 0xb8>,
                            <&cpg CPG_MOD 0xb9>,
                            <&cpg CPG_MOD 0xba>,
                            <&cpg CPG_MOD 0xbb>;
             clock-names = "stmmaceth", "pclk", "ptp_ref",
                                "tx", "rx", "tx-180", "rx-180";
             resets = <&cpg 0xb0>;
             .....
};

Cheers,
Prabhakar