netdev - Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas RZ/V2H(P) SoC

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Message-ID: <CA+V-a8up3Kv08sNarvC3gWLRpik3=_aKb3JCTGkxyGYMcj4Wbg@mail.gmail.com>
Date: Sun, 2 Mar 2025 21:22:52 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Andrew Lunn <andrew@...n.ch>, Geert Uytterhoeven <geert+renesas@...der.be>, 
	Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Giuseppe Cavallaro <peppe.cavallaro@...com>, 
	Jose Abreu <joabreu@...opsys.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, 
	netdev@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas
 RZ/V2H(P) SoC

Hi Russell,

On Sun, Mar 2, 2025 at 9:01 PM Russell King (Oracle)
<linux@...linux.org.uk> wrote:
>
> On Sun, Mar 02, 2025 at 08:41:39PM +0000, Lad, Prabhakar wrote:
> > Hi Andrew,
> >
> > On Sun, Mar 2, 2025 at 7:25 PM Andrew Lunn <andrew@...n.ch> wrote:
> > >
> > > > +  clock-names:
> > > > +    items:
> > > > +      - const: stmmaceth
> > > > +      - const: pclk
> > > > +      - const: ptp_ref
> > > > +      - const: tx
> > > > +      - const: rx
> > > > +      - const: tx-180
> > > > +      - const: rx-180
> > >
> > > As Russell said in an older thread, tx and tx-180 are effectively the
> > > same clock, but with an inverter added. You should be able to arrange
> > > the clock tree that if you enable tx, it also enables tx-180 as a
> > > parent/sibling relationship.
> > >
> > I can certainly do that, but not sure in the DT we will be describing
> > the HW correctly then. I'll have to hide *-180  clocks In the DT and
> > handle and turning on/off these clocks in the clock driver.
> ...
> >              clocks =  <&cpg CPG_MOD 0xbd>,
> >                             <&cpg CPG_MOD 0xbc>,
> >                             <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
> >                             <&cpg CPG_MOD 0xb8>,
> >                             <&cpg CPG_MOD 0xb9>,
> >                             <&cpg CPG_MOD 0xba>,
> >                             <&cpg CPG_MOD 0xbb>;
>
> Your SoC designer really implemented the 0° and 180° as two separate
> independently controllable clocks?
>
Yes there are separate bits to turn ON/OFF the 0° and 180° clocks.

Cheers,
Prabhakar