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Message-ID: <8548aa3d-9904-47b8-b5e0-869785c2330d@amd.com>
Date: Tue, 11 Mar 2025 15:05:29 -0500
From: Ben Cheatham <benjamin.cheatham@....com>
To: <alejandro.lucero-palau@....com>
CC: <linux-cxl@...r.kernel.org>, <netdev@...r.kernel.org>,
<dan.j.williams@...el.com>, <edward.cree@....com>, <davem@...emloft.net>,
<kuba@...nel.org>, <pabeni@...hat.com>, <edumazet@...gle.com>,
<dave.jiang@...el.com>, <benjamin.cheatham@....com>
Subject: Re: [PATCH v11 04/23] cxl: move register/capability check to driver
On 3/10/25 4:03 PM, alejandro.lucero-palau@....com wrote:
> From: Alejandro Lucero <alucerop@....com>
>
> Type3 has some mandatory capabilities which are optional for Type2.
>
> In order to support same register/capability discovery code for both
> types, avoid any assumption about what capabilities should be there, and
> export the capabilities found for the caller doing the capabilities
> check based on the expected ones.
>
> Signed-off-by: Alejandro Lucero <alucerop@....com>
> ---
> drivers/cxl/core/pci.c | 4 ++--
> drivers/cxl/core/port.c | 8 ++++----
> drivers/cxl/core/regs.c | 37 +++++++++++++++++++++----------------
> drivers/cxl/cxl.h | 6 +++---
> drivers/cxl/cxlpci.h | 2 +-
> drivers/cxl/pci.c | 31 ++++++++++++++++++++++++++++---
> include/cxl/cxl.h | 20 ++++++++++++++++++++
> 7 files changed, 79 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 0b8dc34b8300..05399292209a 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -1061,7 +1061,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
> }
>
> int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map)
> + struct cxl_register_map *map, unsigned long *caps)
> {
> int rc;
>
> @@ -1091,7 +1091,7 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> return rc;
> }
>
> - return cxl_setup_regs(map);
> + return cxl_setup_regs(map, caps);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 6a44b6dad3c7..ede36f7168ed 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -755,7 +755,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> }
>
> static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
> - resource_size_t component_reg_phys)
> + resource_size_t component_reg_phys, unsigned long *caps)
> {
> *map = (struct cxl_register_map) {
> .host = host,
> @@ -769,7 +769,7 @@ static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map
> map->reg_type = CXL_REGLOC_RBI_COMPONENT;
> map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
>
> - return cxl_setup_regs(map);
> + return cxl_setup_regs(map, caps);
> }
>
> static int cxl_port_setup_regs(struct cxl_port *port,
> @@ -778,7 +778,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
> if (dev_is_platform(port->uport_dev))
> return 0;
> return cxl_setup_comp_regs(&port->dev, &port->reg_map,
> - component_reg_phys);
> + component_reg_phys, NULL);
> }
>
> static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
> @@ -795,7 +795,7 @@ static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
> * NULL.
> */
> rc = cxl_setup_comp_regs(dport->dport_dev, &dport->reg_map,
> - component_reg_phys);
> + component_reg_phys, NULL);
Nit here, but if you just pass in a unsigned long here, and in cxl_port_setup_regs() above, instead of NULL
you can get rid of the null pointer checks in the register probe functions.
> dport->reg_map.host = host;
> return rc;
> }
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index be0ae9aca84a..4a3a462bd313 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -4,6 +4,7 @@
> #include <linux/device.h>
> #include <linux/slab.h>
> #include <linux/pci.h>
> +#include <cxl/cxl.h>
> #include <cxl/pci.h>
> #include <cxlmem.h>
> #include <cxlpci.h>
> @@ -30,6 +31,7 @@
> * @dev: Host device of the @base mapping
> * @base: Mapping containing the HDM Decoder Capability Header
> * @map: Map object describing the register block information found
> + * @caps: capabilities to be set when discovered
> *
> * See CXL 2.0 8.2.4 Component Register Layout and Definition
> * See CXL 2.0 8.2.5.5 CXL Device Register Interface
> @@ -37,7 +39,8 @@
> * Probe for component register information and return it in map object.
> */
> void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> - struct cxl_component_reg_map *map)
> + struct cxl_component_reg_map *map,
> + unsigned long *caps)
> {
> int cap, cap_count;
> u32 cap_array;
> @@ -85,6 +88,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> decoder_cnt = cxl_hdm_decoder_count(hdr);
> length = 0x20 * decoder_cnt + 0x10;
> rmap = &map->hdm_decoder;
> + if (caps)
> + set_bit(CXL_DEV_CAP_HDM, caps);
With above change, this check and the ones below go away.
> break;
> }
> case CXL_CM_CAP_CAP_ID_RAS:
> @@ -92,6 +97,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> offset);
> length = CXL_RAS_CAPABILITY_LENGTH;
> rmap = &map->ras;
> + if (caps)
> + set_bit(CXL_DEV_CAP_RAS, caps);
> break;
> default:
> dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
> @@ -114,11 +121,12 @@ EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, "CXL");
> * @dev: Host device of the @base mapping
> * @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
> * @map: Map object describing the register block information found
> + * @caps: capabilities to be set when discovered
> *
> * Probe for device register information and return it in map object.
> */
> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> - struct cxl_device_reg_map *map)
> + struct cxl_device_reg_map *map, unsigned long *caps)
> {
> int cap, cap_count;
> u64 cap_array;
> @@ -147,10 +155,14 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
> dev_dbg(dev, "found Status capability (0x%x)\n", offset);
> rmap = &map->status;
> + if (caps)
> + set_bit(CXL_DEV_CAP_DEV_STATUS, caps);
> break;
> case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
> dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
> rmap = &map->mbox;
> + if (caps)
> + set_bit(CXL_DEV_CAP_MAILBOX_PRIMARY, caps);
> break;
> case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
> dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
> @@ -158,6 +170,8 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> case CXLDEV_CAP_CAP_ID_MEMDEV:
> dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
> rmap = &map->memdev;
> + if (caps)
> + set_bit(CXL_DEV_CAP_MEMDEV, caps);
> break;
> default:
> if (cap_id >= 0x8000)
> @@ -434,7 +448,7 @@ static void cxl_unmap_regblock(struct cxl_register_map *map)
> map->base = NULL;
> }
>
> -static int cxl_probe_regs(struct cxl_register_map *map)
> +static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> @@ -444,21 +458,12 @@ static int cxl_probe_regs(struct cxl_register_map *map)
> switch (map->reg_type) {
> case CXL_REGLOC_RBI_COMPONENT:
> comp_map = &map->component_map;
> - cxl_probe_component_regs(host, base, comp_map);
> + cxl_probe_component_regs(host, base, comp_map, caps);
> dev_dbg(host, "Set up component registers\n");
> break;
> case CXL_REGLOC_RBI_MEMDEV:
> dev_map = &map->device_map;
> - cxl_probe_device_regs(host, base, dev_map);
> - if (!dev_map->status.valid || !dev_map->mbox.valid ||
> - !dev_map->memdev.valid) {
> - dev_err(host, "registers not found: %s%s%s\n",
> - !dev_map->status.valid ? "status " : "",
> - !dev_map->mbox.valid ? "mbox " : "",
> - !dev_map->memdev.valid ? "memdev " : "");
> - return -ENXIO;
> - }
> -
> + cxl_probe_device_regs(host, base, dev_map, caps);
> dev_dbg(host, "Probing device registers...\n");
> break;
> default:
> @@ -468,7 +473,7 @@ static int cxl_probe_regs(struct cxl_register_map *map)
> return 0;
> }
>
> -int cxl_setup_regs(struct cxl_register_map *map)
> +int cxl_setup_regs(struct cxl_register_map *map, unsigned long *caps)
> {
> int rc;
>
> @@ -476,7 +481,7 @@ int cxl_setup_regs(struct cxl_register_map *map)
> if (rc)
> return rc;
>
> - rc = cxl_probe_regs(map);
> + rc = cxl_probe_regs(map, caps);
> cxl_unmap_regblock(map);
>
> return rc;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 5d608975ca38..4523864eebd2 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -202,9 +202,9 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
> #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
>
> void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> - struct cxl_component_reg_map *map);
> + struct cxl_component_reg_map *map, unsigned long *caps);
> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> - struct cxl_device_reg_map *map);
> + struct cxl_device_reg_map *map, unsigned long *caps);
> int cxl_map_component_regs(const struct cxl_register_map *map,
> struct cxl_component_regs *regs,
> unsigned long map_mask);
> @@ -219,7 +219,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
> struct cxl_register_map *map, unsigned int index);
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> struct cxl_register_map *map);
> -int cxl_setup_regs(struct cxl_register_map *map);
> +int cxl_setup_regs(struct cxl_register_map *map, unsigned long *caps);
> struct cxl_dport;
> int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
>
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 0611d96d76da..e003495295a0 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -115,5 +115,5 @@ void cxl_cor_error_detected(struct pci_dev *pdev);
> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> pci_channel_state_t state);
> int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map);
> + struct cxl_register_map *map, unsigned long *caps);
> #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index e8c0efb3a12f..17ac28baa52c 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -836,6 +836,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> {
> struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
> struct cxl_dpa_info range_info = { 0 };
> + DECLARE_BITMAP(expected, CXL_MAX_CAPS);
> + DECLARE_BITMAP(found, CXL_MAX_CAPS);
> struct cxl_memdev_state *mds;
> struct cxl_dev_state *cxlds;
> struct cxl_register_map map;
> @@ -871,7 +873,19 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>
> cxlds->rcd = is_cxl_restricted(pdev);
>
> - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
> + bitmap_zero(expected, CXL_MAX_CAPS);
> + bitmap_zero(found, CXL_MAX_CAPS);
> +
> + /*
> + * These are the mandatory capabilities for a Type3 device.
> + * Only checking capabilities used by current Linux drivers.
> + */
> + set_bit(CXL_DEV_CAP_HDM, expected);
> + set_bit(CXL_DEV_CAP_DEV_STATUS, expected);
> + set_bit(CXL_DEV_CAP_MAILBOX_PRIMARY, expected);
> + set_bit(CXL_DEV_CAP_MEMDEV, expected);
> +
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, found);
> if (rc)
> return rc;
>
> @@ -883,8 +897,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> * If the component registers can't be found, the cxl_pci driver may
> * still be useful for management functions so don't return an error.
> */
> - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
> - &cxlds->reg_map);
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &cxlds->reg_map,
> + found);
> if (rc)
> dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
> else if (!cxlds->reg_map.component_map.ras.valid)
> @@ -895,6 +909,17 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
>
> + /*
> + * Checking mandatory caps are there as, at least, a subset of those
> + * found.
> + */
> + if (!bitmap_subset(expected, found, CXL_MAX_CAPS)) {
> + dev_err(&pdev->dev,
> + "Expected mandatory capabilities not found: (%pb - %pb)\n",
I think this will just print the bitmaps, so it would probably be good to highlight which is
the mandatory capabilites map and which is the found. Maybe something like:
"Found capabilities (%pb) are missing mandatory capabilities (%pb)\n"
> + expected, found);
> + return -ENXIO;
> + }
> +
> rc = cxl_pci_type3_init_mailbox(cxlds);
> if (rc)
> return rc;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 5c6481136f93..02b73c82e5d8 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -25,6 +25,26 @@ enum cxl_devtype {
>
> struct device;
>
> +
> +/* Capabilities as defined for:
> + *
> + * Component Registers (Table 8-22 CXL 3.1 specification)
> + * Device Registers (8.2.8.2.1 CXL 3.1 specification)
Update to 3.2 spec?
> + *
> + * and currently being used for kernel CXL support.
> + */
> +
> +enum cxl_dev_cap {
> + /* capabilities from Component Registers */
> + CXL_DEV_CAP_RAS,
> + CXL_DEV_CAP_HDM,
> + /* capabilities from Device Registers */
> + CXL_DEV_CAP_DEV_STATUS,
> + CXL_DEV_CAP_MAILBOX_PRIMARY,
> + CXL_DEV_CAP_MEMDEV,
> + CXL_MAX_CAPS,
> +};
> +
> /*
> * Using struct_group() allows for per register-block-type helper routines,
> * without requiring block-type agnostic code to include the prefix.
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