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Message-ID: <ce0796f4-cf2e-4a3d-ae79-1f9b9966773e@lunn.ch>
Date: Wed, 12 Mar 2025 20:02:15 +0100
From: Andrew Lunn <andrew@...n.ch>
To: "Gupta, Suraj" <Suraj.Gupta2@....com>
Cc: Russell King <linux@...linux.org.uk>,
"Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>,
"andrew+netdev@...n.ch" <andrew+netdev@...n.ch>,
"davem@...emloft.net" <davem@...emloft.net>,
"edumazet@...gle.com" <edumazet@...gle.com>,
"kuba@...nel.org" <kuba@...nel.org>,
"pabeni@...hat.com" <pabeni@...hat.com>,
"robh@...nel.org" <robh@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>,
"Simek, Michal" <michal.simek@....com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
"git (AMD-Xilinx)" <git@....com>,
"Katakam, Harini" <harini.katakam@....com>
Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X
only configuration.
On Wed, Mar 12, 2025 at 04:08:02PM +0000, Gupta, Suraj wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> > -----Original Message-----
> > From: Andrew Lunn <andrew@...n.ch>
> > Sent: Wednesday, March 12, 2025 9:03 PM
> > To: Gupta, Suraj <Suraj.Gupta2@....com>
> > Cc: Russell King <linux@...linux.org.uk>; Pandey, Radhey Shyam
> > <radhey.shyam.pandey@....com>; andrew+netdev@...n.ch;
> > davem@...emloft.net; edumazet@...gle.com; kuba@...nel.org;
> > pabeni@...hat.com; robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org;
> > Simek, Michal <michal.simek@....com>; netdev@...r.kernel.org;
> > devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-arm-
> > kernel@...ts.infradead.org; git (AMD-Xilinx) <git@....com>; Katakam, Harini
> > <harini.katakam@....com>
> > Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only
> > configuration.
> >
> > Caution: This message originated from an External Source. Use proper caution
> > when opening attachments, clicking links, or responding.
> >
> >
> > On Wed, Mar 12, 2025 at 03:06:32PM +0000, Gupta, Suraj wrote:
> > > [AMD Official Use Only - AMD Internal Distribution Only]
> > >
> > > > -----Original Message-----
> > > > From: Andrew Lunn <andrew@...n.ch>
> > > > Sent: Wednesday, March 12, 2025 8:29 PM
> > > > To: Gupta, Suraj <Suraj.Gupta2@....com>
> > > > Cc: Russell King <linux@...linux.org.uk>; Pandey, Radhey Shyam
> > > > <radhey.shyam.pandey@....com>; andrew+netdev@...n.ch;
> > > > davem@...emloft.net; edumazet@...gle.com; kuba@...nel.org;
> > > > pabeni@...hat.com; robh@...nel.org; krzk+dt@...nel.org;
> > > > conor+dt@...nel.org; Simek, Michal <michal.simek@....com>;
> > > > netdev@...r.kernel.org; devicetree@...r.kernel.org;
> > > > linux-kernel@...r.kernel.org; linux-arm- kernel@...ts.infradead.org;
> > > > git (AMD-Xilinx) <git@....com>; Katakam, Harini
> > > > <harini.katakam@....com>
> > > > Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for
> > > > 2500base-X only configuration.
> > > >
> > > > Caution: This message originated from an External Source. Use proper
> > > > caution when opening attachments, clicking links, or responding.
> > > >
> > > >
> > > > > > On Wed, Mar 12, 2025 at 02:25:27PM +0100, Andrew Lunn wrote:
> > > > > > > > + /* AXI 1G/2.5G ethernet IP has following synthesis options:
> > > > > > > > + * 1) SGMII/1000base-X only.
> > > > > > > > + * 2) 2500base-X only.
> > > > > > > > + * 3) Dynamically switching between (1) and (2), and is not
> > > > > > > > + * implemented in driver.
> > > > > > > > + */
> > > >
> > > > > - Keeping previous discussion short, identification of (3) depends
> > > > > on how user implements switching logic in FPGA (external GT or RTL
> > > > > logic). AXI 1G/2.5G IP provides only static speed selections and
> > > > > there is no standard register to communicate that to software.
> > > >
> > > > So if anybody has synthesised it as 3) this change will break their system?
> > > >
> > > > Andrew
> > >
> > > It will just restrict their system to (2)
> >
> > Where as before, it was doing SGMII/1000base-X only. So such systems break?
> >
> > Andrew
>
> If the user wants (3), they need to add their custom FPGA logic
> which anyway will require additional driver changes. (3) was not
> completely supported by existing driver.
You say 3) is a synthesis option. Say somebody synthesised it that
way, and found it works for what they need with SGMII/1000base-X.
Because the driver took no notice of the capability bit, that is what
it would do. Since it worked for them, they might not of gone back and
optimised the options. "If it is not broken, don't fix it". So we
could have systems out in the wild, synthesised as 3) happily doing
SGMII/1000base-X ?
With this change, won't you break those systems?
I'm just trying to get to a definitive answer, is this change actually
safe to all todays possible systems?
Andrew
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