netdev - Re: [PATCH v11 03/23] cxl: move pci generic code

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Message-ID: <98361e3f-e2f8-43c2-a032-f7e84d5414e0@amd.com>
Date: Wed, 12 Mar 2025 08:26:33 +0000
From: Alejandro Lucero Palau <alucerop@....com>
To: Ben Cheatham <benjamin.cheatham@....com>, alejandro.lucero-palau@....com
Cc: Fan Ni <fan.ni@...sung.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>, linux-cxl@...r.kernel.org,
 netdev@...r.kernel.org, dan.j.williams@...el.com, edward.cree@....com,
 davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com,
 edumazet@...gle.com, dave.jiang@...el.com
Subject: Re: [PATCH v11 03/23] cxl: move pci generic code


On 3/11/25 20:05, Ben Cheatham wrote:
> On 3/10/25 4:03 PM, alejandro.lucero-palau@....com wrote:
>> From: Alejandro Lucero <alucerop@....com>
>>
>> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization
>> meanwhile cxl/pci.c implements the functionality for a Type3 device
>> initialization.
>>
>> Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be
>> exported and shared with CXL Type2 device initialization.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> Reviewed-by: Dave Jiang <dave.jiang@...el.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
>> Reviewed-by: Fan Ni <fan.ni@...sung.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>> ---
> [snip]
>
>> diff --git a/include/cxl/pci.h b/include/cxl/pci.h
>> index ad63560caa2c..e6178aa341b2 100644
>> --- a/include/cxl/pci.h
>> +++ b/include/cxl/pci.h
>> @@ -1,8 +1,21 @@
>>   /* SPDX-License-Identifier: GPL-2.0-only */
>>   /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
>>   
>> -#ifndef __CXL_ACCEL_PCI_H
>> -#define __CXL_ACCEL_PCI_H
>> +#ifndef __LINUX_CXL_PCI_H
>> +#define __LINUX_CXL_PCI_H
> Should probably just change this to __LINUX_CXL_PCI_H in the last patch
> when creating the file.


Yes, this is biting me again.

I'll do so.

Thanks


> With that:
> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
>
>> +
>> +#include <linux/pci.h>
>> +
>> +/*
>> + * Assume that the caller has already validated that @pdev has CXL
>> + * capabilities, any RCIEp with CXL capabilities is treated as a
>> + * Restricted CXL Device (RCD) and finds upstream port and endpoint
>> + * registers in a Root Complex Register Block (RCRB).
>> + */
>> +static inline bool is_cxl_restricted(struct pci_dev *pdev)
>> +{
>> +	return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
>> +}
>>   
>>   /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
>>   #define CXL_DVSEC_PCIE_DEVICE					0
>> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
>> index ef10a896a384..f20df22bddd2 100644
>> --- a/tools/testing/cxl/Kbuild
>> +++ b/tools/testing/cxl/Kbuild
>> @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready
>>   ldflags-y += --wrap=cxl_hdm_decode_init
>>   ldflags-y += --wrap=cxl_dvsec_rr_decode
>>   ldflags-y += --wrap=devm_cxl_add_rch_dport
>> -ldflags-y += --wrap=cxl_rcd_component_reg_phys
>>   ldflags-y += --wrap=cxl_endpoint_parse_cdat
>>   ldflags-y += --wrap=cxl_dport_init_ras_reporting
>>   
>> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
>> index af2594e4f35d..3c6a071fbbe3 100644
>> --- a/tools/testing/cxl/test/mock.c
>> +++ b/tools/testing/cxl/test/mock.c
>> @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port,
>>   }
>>   EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL");
>>   
>> -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev,
>> -						  struct cxl_dport *dport)
>> -{
>> -	int index;
>> -	resource_size_t component_reg_phys;
>> -	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>> -
>> -	if (ops && ops->is_mock_port(dev))
>> -		component_reg_phys = CXL_RESOURCE_NONE;
>> -	else
>> -		component_reg_phys = cxl_rcd_component_reg_phys(dev, dport);
>> -	put_cxl_mock_ops(index);
>> -
>> -	return component_reg_phys;
>> -}
>> -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL");
>> -
>>   void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port)
>>   {
>>   	int index;