netdev - RE: [PATCH RFC net-next 0/4] net: xpcs: cleanups and partial support for KSZ9477

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Message-ID:
 <DM3PR11MB8736D45A311DA7C448825BABECDE2@DM3PR11MB8736.namprd11.prod.outlook.com>
Date: Tue, 18 Mar 2025 19:59:07 +0000
From: <Tristram.Ha@...rochip.com>
To: <linux@...linux.org.uk>
CC: <andrew@...n.ch>, <davem@...emloft.net>, <edumazet@...gle.com>,
	<hkallweit1@...il.com>, <kuba@...nel.org>, <netdev@...r.kernel.org>,
	<pabeni@...hat.com>, <UNGLinuxDriver@...rochip.com>, <olteanv@...il.com>,
	<Woojung.Huh@...rochip.com>
Subject: RE: [PATCH RFC net-next 0/4] net: xpcs: cleanups and partial support
 for KSZ9477

> Subject: Re: [PATCH RFC net-next 0/4] net: xpcs: cleanups and partial support for
> KSZ9477
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content
> is safe
> 
> On Wed, Feb 05, 2025 at 01:27:26PM +0000, Russell King (Oracle) wrote:
> > Work for Microchip to do before this series can be merged:
> >
> > 1. work out how to identify their XPCS integration from other
> >    integrations, so allowing MAC_MANUAL SGMII mode to be selected.
> 
> This is now complete.
> 
> > 2. verify where the requirement for setting the two bits for 1000BASE-X
> >    has come from (from what Jose has said, we don't believe it's from
> >    Synopsys.)
> 
> I believe this is still outstanding - and is a question that Vladimir
> asked of you quite a while ago. What is the status of this?
> 
> Until this is answered, we can't move forward with these patches
> unless Vladimir is now happy to accept them given Jose's response.
> Vladimir seemed to be quite adamant that this needed to be answered.

Sorry for the long delay.  After discussing with the Microchip design
team we come up with this explanation for setting the
DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII (bit 3) of DW_VR_MII_AN_CTRL (0x8001)
register in 1000Base-X mode to make it work with AN on.

KSZ9477 has the older version of 1000Base-X Synopsys IP which works in
1000Base-X mode without AN.  When AN is on the port does not pass traffic
because it does not detect a link.  Setting
DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII allows the link to be turned on by
either setting DW_VR_MII_SGMII_LINK_STS (bit 4) or
DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL (bit 0) in DW_VR_MII_DIG_CTRL1 (0x8000)
register.  After that the port can pass traffic.

This is still a specific KSZ9477 problem so it may be safer to put this
code under "if (xpcs->info.pma == MICROCHIP_KSZ9477_PMD_ID)" check.