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Message-ID: <37629e9c-0a9f-4e08-921c-efbf7824c371@linux.dev>
Date: Thu, 20 Mar 2025 16:21:57 +0000
From: Vadim Fedorenko <vadim.fedorenko@...ux.dev>
To: Andrew Lunn <andrew@...n.ch>, Pavan Chebbi <pavan.chebbi@...adcom.com>,
Kamil Zaripov <zaripov-kamil@...ide.ai>
Cc: netdev@...r.kernel.org, Michael Chan <michael.chan@...adcom.com>,
Andrew Gospodarek <andrew.gospodarek@...adcom.com>
Subject: Re: bnxt_en: Incorrect tx timestamp report
On 20/03/2025 14:48, Andrew Lunn wrote:
>> 2. Is there a method available to read the complete 64-bit PHC
>> counter to mitigate the observed problem of 2^48-nanosecond time
>> jumps?
>
> The usual workaround is to read the upper part, the lower part, and
> the upper part again. If you get two different values for the upper
> part, do it all again, until you get consistent values.
>
> Look around other PTP drivers, there is probably code you can
> copy/paste.
This part of the driver is tricky. ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE
reports only 16 bits of 64 bits timestamp, 48-63 range, which doesn't
overlap with anything else. The assumption is that when the driver
processes this event, the register which reports bits of range 0-47 has
already overflowed and holds new value. Unfortunately, there is a time
gap between register overflow and update of MSB of the cached timestamp.
There is no easy way to solve this problem, but we may add additional
check on every read, probably... Not sure, though
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