| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <2a220c71a7428dd38a18ebd17408f4d7d8e0cc33.camel@hazent.com>
Date: Mon, 07 Apr 2025 10:57:39 +0200
From: Álvaro "G. M." <alvaro.gamez@...ent.com>
To: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, Jakub Kicinski
<kuba@...nel.org>, "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>
Subject: Re: Fwd: Re: Issue with AMD Xilinx AXI Ethernet (xilinx_axienet) on
MicroBlaze: Packets only received after some buffer is full
Hi again
> On Thu, 2025-04-03 at 13:58 +0000, Gupta, Suraj wrote:
> >
> >
> > FYI, basic ping and iperf both works for us in DMAengine flow for AXI ethernet
> > 1G designs. We tested for full-duplex mode. But I can see half duplex in your case,
> > could you please confirm if that is expected and correct?
I've implemented a very basic block diagram on Vivado for Digilent Nexys Video board,
which fits a 1G phy from realtek. The behaviour is exactly the same: using dmaengine
makes it so that a great big chunk of data needs to arrive before it reaches the kernel,
whereas using old dma code in axienet.c, even though doesn't have that buffering effect,
still drops ARP request packets.
The exact same design works in the same kernel I had running on my board, 4.4.43
If you have this tested on other boards, I must assume it's just a matter of my DTS
being defective, so I'm attaching the whole thing here alongside kernel config,
and I've created a github repo with the buildroot and Vivado projects in case you
want to take a look at them: https://github.com/agamez/axinet_debug, but it's
simply the basics. I've included snapshots of DMA and ethernet configuration
in the repository so you don't even need to create it if you don't want to.
# ifconfig eth0 192.168.99.2
xilinx_axienet 40c00000.ethernet eth0: PHY [axienet-40c00000:01] driver [RTL8211E Gigabit Ethernet] (irq=POLL)
xilinx_axienet 40c00000.ethernet eth0: configuring for phy/rgmii link mode
xilinx_axienet 40c00000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
# ifconfig eth0
eth0 Link encap:Ethernet HWaddr 02:10:20:30:40:50
inet addr:192.168.99.2 Bcast:192.168.99.255 Mask:255.255.255.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:2 errors:0 dropped:2 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:340 (340.0 B) TX bytes:0 (0.0 B)
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,microblaze";
model = "Xilinx MicroBlaze";
cpus {
#address-cells = <1>;
#cpus = <1>;
#size-cells = <0>;
microblaze_0: cpu@0 {
reg = <0>;
bus-handle = <&amba_pl>;
clock-frequency = <100000000>;
clocks = <&clk_cpu>;
compatible = "xlnx,microblaze-9.5";
d-cache-baseaddr = <0x80000000>;
d-cache-highaddr = <0x8fffffff>;
d-cache-line-size = <0x10>;
d-cache-size = <0x8000>;
device_type = "cpu";
i-cache-baseaddr = <0x80000000>;
i-cache-highaddr = <0x8fffffff>;
i-cache-line-size = <0x20>;
i-cache-size = <0x8000>;
interrupt-handle = <µblaze_0_axi_intc>;
model = "microblaze,9.5";
timebase-frequency = <100000000>;
xlnx,addr-tag-bits = <0xd>;
xlnx,allow-dcache-wr = <0x1>;
xlnx,allow-icache-wr = <0x1>;
xlnx,area-optimized = <0x0>;
xlnx,async-interrupt = <0x1>;
xlnx,avoid-primitives = <0x0>;
xlnx,base-vectors = <0x00000000>;
xlnx,branch-target-cache-size = <0x0>;
xlnx,cache-byte-size = <0x8000>;
xlnx,d-axi = <0x1>;
xlnx,d-lmb = <0x1>;
xlnx,d-lmb-mon = <0x0>;
xlnx,data-size = <0x20>;
xlnx,dc-axi-mon = <0x0>;
xlnx,dcache-addr-tag = <0xd>;
xlnx,dcache-always-used = <0x1>;
xlnx,dcache-byte-size = <0x8000>;
xlnx,dcache-data-width = <0x0>;
xlnx,dcache-force-tag-lutram = <0x0>;
xlnx,dcache-line-len = <0x4>;
xlnx,dcache-use-writeback = <0x0>;
xlnx,dcache-victims = <0x8>;
xlnx,debug-counter-width = <0x20>;
xlnx,debug-enabled = <0x1>;
xlnx,debug-event-counters = <0x5>;
xlnx,debug-external-trace = <0x0>;
xlnx,debug-latency-counters = <0x1>;
xlnx,debug-profile-size = <0x0>;
xlnx,debug-trace-size = <0x2000>;
xlnx,div-zero-exception = <0x1>;
xlnx,dp-axi-mon = <0x0>;
xlnx,dynamic-bus-sizing = <0x0>;
xlnx,ecc-use-ce-exception = <0x0>;
xlnx,edge-is-positive = <0x1>;
xlnx,enable-discrete-ports = <0x0>;
xlnx,endianness = <0x1>;
xlnx,fault-tolerant = <0x0>;
xlnx,fpu-exception = <0x0>;
xlnx,freq = <0x4f64b50>;
xlnx,fsl-exception = <0x0>;
xlnx,fsl-links = <0x0>;
xlnx,i-axi = <0x0>;
xlnx,i-lmb = <0x1>;
xlnx,i-lmb-mon = <0x0>;
xlnx,ic-axi-mon = <0x0>;
xlnx,icache-always-used = <0x1>;
xlnx,icache-data-width = <0x0>;
xlnx,icache-force-tag-lutram = <0x0>;
xlnx,icache-line-len = <0x8>;
xlnx,icache-streams = <0x1>;
xlnx,icache-victims = <0x8>;
xlnx,ill-opcode-exception = <0x1>;
xlnx,imprecise-exceptions = <0x0>;
xlnx,interconnect = <0x2>;
xlnx,interrupt-is-edge = <0x0>;
xlnx,interrupt-mon = <0x0>;
xlnx,ip-axi-mon = <0x0>;
xlnx,lockstep-select = <0x0>;
xlnx,lockstep-slave = <0x0>;
xlnx,mmu-dtlb-size = <0x4>;
xlnx,mmu-itlb-size = <0x2>;
xlnx,mmu-privileged-instr = <0x0>;
xlnx,mmu-tlb-access = <0x3>;
xlnx,mmu-zones = <0x2>;
xlnx,num-sync-ff-clk = <0x2>;
xlnx,num-sync-ff-clk-debug = <0x2>;
xlnx,num-sync-ff-clk-irq = <0x1>;
xlnx,num-sync-ff-dbg-clk = <0x1>;
xlnx,number-of-pc-brk = <0x1>;
xlnx,number-of-rd-addr-brk = <0x0>;
xlnx,number-of-wr-addr-brk = <0x0>;
xlnx,opcode-0x0-illegal = <0x1>;
xlnx,optimization = <0x0>;
xlnx,pc-width = <0x20>;
xlnx,pvr = <0x2>;
xlnx,pvr-user1 = <0x00>;
xlnx,pvr-user2 = <0x00000000>;
xlnx,reset-msr = <0x00000000>;
xlnx,sco = <0x0>;
xlnx,trace = <0x0>;
xlnx,unaligned-exceptions = <0x1>;
xlnx,use-barrel = <0x1>;
xlnx,use-branch-target-cache = <0x0>;
xlnx,use-config-reset = <0x0>;
xlnx,use-dcache = <0x1>;
xlnx,use-div = <0x1>;
xlnx,use-ext-brk = <0x0>;
xlnx,use-ext-nm-brk = <0x0>;
xlnx,use-extended-fsl-instr = <0x0>;
xlnx,use-fpu = <0x0>;
xlnx,use-hw-mul = <0x2>;
xlnx,use-icache = <0x1>;
xlnx,use-interrupt = <0x2>;
xlnx,use-mmu = <0x3>;
xlnx,use-msr-instr = <0x1>;
xlnx,use-pcmp-instr = <0x1>;
xlnx,use-reorder-instr = <0x1>;
xlnx,use-stack-protection = <0x0>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
clk_cpu: clk_cpu@0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "clk_cpu";
compatible = "fixed-clock";
reg = <0>;
};
clk_bus_0: clk_bus_0@1 {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "clk_bus_0";
compatible = "fixed-clock";
reg = <1>;
};
};
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
microblaze_0_axi_intc: interrupt-controller@...00000 {
#interrupt-cells = <2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = <0x41200000 0x10000>;
xlnx,kind-of-intr = <0x06>;
xlnx,num-intr-inputs = <0x06>;
};
axi_timer_0: timer@...00000 {
clock-frequency = <100000000>;
clocks = <&clk_bus_0>;
compatible = "xlnx,xps-timer-1.00.a";
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <0 2>;
reg = <0x41c00000 0x10000>;
xlnx,count-width = <0x20>;
xlnx,gen0-assert = <0x1>;
xlnx,gen1-assert = <0x1>;
xlnx,one-timer-only = <0x0>;
xlnx,trig0-assert = <0x1>;
xlnx,trig1-assert = <0x1>;
};
axi_uartlite_0: serial@...00000 {
clock-frequency = <100000000>;
clocks = <&clk_bus_0>;
compatible = "xlnx,xps-uartlite-1.00.a";
current-speed = <115200>;
device_type = "serial";
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <1 0>;
port-number = <0>;
reg = <0x40600000 0x10000>;
xlnx,baudrate = <0x2580>;
xlnx,data-bits = <0x8>;
xlnx,odd-parity = <0x0>;
xlnx,s-axi-aclk-freq-hz-d = "100.00";
xlnx,use-parity = <0x0>;
};
axi_ethernet_0_dma: dma@...00000 {
compatible = "xlnx,axi-dma-1.00.a";
#dma-cells = <1>;
reg = <0x41e00000 0x10000>;
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <4 1 5 1>;
xlnx,addrwidth = <32>;
xlnx,datawidth = <32>;
xlnx,include-sg;
xlnx,sg-length-width = <16>;
xlnx,include-dre = <1>;
xlnx,axistream-connected = <1>;
xlnx,irq-delay = <0>;
dma-channels = <2>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>;
dma-channel@...00000 {
compatible = "xlnx,axi-dma-mm2s-channel";
xlnx,include-dre = <1>;
interrupts = <4 1>;
xlnx,datawidth = <32>;
};
dma-channel@...00030 {
compatible = "xlnx,axi-dma-s2mm-channel";
xlnx,include-dre = <1>;
interrupts = <5 1>;
xlnx,datawidth = <32>;
};
};
axi_ethernet_eth: ethernet@...00000 {
compatible = "xlnx,axi-ethernet-1.00.a";
reg = <0x40c00000 0x40000>;
phy-handle = <&phy1>;
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <3 0>;
xlnx,rxmem = <0x8000>;
max-speed = <100000>;
phy-mode = "rgmii";
xlnx,txcsum = <0x2>;
xlnx,rxcsum = <0x2>;
clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
clocks = <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>;
axistream-connected = <&axi_ethernet_0_dma>;
dmas = <&axi_ethernet_0_dma 0>, <&axi_ethernet_0_dma 1>;
dma-names = "tx_chan0", "rx_chan0";
axi_ethernetlite_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
/* compatible = "ethernet-phy-id001c.c915", "realtek,RTL8211E", "ethernet-phy-ieee802.3-c22"; */
device_type = "ethernet-phy";
reg = <1>;
};
};
};
};
};
/ {
chosen {
bootargs = "console=ttyUL0,9600 uio_pdrv_genirq.of_id=generic-uio";
linux,stdout-path = &axi_uartlite_0;
stdout-path = &axi_uartlite_0;
};
aliases {
serial0 = &axi_uartlite_0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x0fffffff>;
};
};
&axi_ethernet_eth {
local-mac-address = [02 10 20 30 40 50];
};
This is my kernel configuration. Buildroot sets later initramfs.
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_KERNEL_BASE_ADDR=0x80000000
CONFIG_XILINX_MICROBLAZE0_FAMILY="artix7"
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2
CONFIG_XILINX_MICROBLAZE0_USE_FPU=2
CONFIG_XILINX_MICROBLAZE0_HW_VER="8.30.a"
CONFIG_HZ_100=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon console=ttyUL0,9600"
CONFIG_HIGHMEM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SPI_NOR=y
CONFIG_NETDEVICES=y
CONFIG_XILINX_AXI_EMAC=y
CONFIG_REALTEK_PHY=y
CONFIG_DP83848_PHY=y
CONFIG_DP83620_PHY=y
CONFIG_DP83869_PHY=y
CONFIG_SERIAL_UARTLITE=y
CONFIG_SERIAL_UARTLITE_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_XILINX=y
CONFIG_SPI=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_XILINX=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y
CONFIG_FB_XILINX=y
CONFIG_DMADEVICES=y
CONFIG_XILINX_DMA=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_IIO=y
CONFIG_AD799X=y
CONFIG_XILINX_XADC=y
CONFIG_JFFS2_FS=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BOTH=y
CONFIG_NFS_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
Thanks a lot,
--
Álvaro G. M.
Powered by blists - more mailing lists