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Message-ID: <8ab734d2-f565-4b6c-910b-4794e5e382b0@amd.com>
Date: Mon, 7 Apr 2025 12:02:38 +0100
From: Alejandro Lucero Palau <alucerop@....com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>,
alejandro.lucero-palau@....com
Cc: linux-cxl@...r.kernel.org, netdev@...r.kernel.org,
dan.j.williams@...el.com, edward.cree@....com, davem@...emloft.net,
kuba@...nel.org, pabeni@...hat.com, edumazet@...gle.com,
dave.jiang@...el.com, Martin Habets <habetsm.xilinx@...il.com>,
Edward Cree <ecree.xilinx@...il.com>
Subject: Re: [PATCH v12 12/23] sfc: obtain root decoder with enough HPA free
space
On 4/4/25 17:38, Jonathan Cameron wrote:
> On Mon, 31 Mar 2025 15:45:44 +0100
> alejandro.lucero-palau@....com wrote:
>
>> From: Alejandro Lucero <alucerop@....com>
>>
>> Asking for available HPA space is the previous step to try to obtain
>> an HPA range suitable to accel driver purposes.
>>
>> Add this call to efx cxl initialization.
>>
>> Make sfc cxl build dependent on CXL region.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>> Reviewed-by: Martin Habets <habetsm.xilinx@...il.com>
>> Acked-by: Edward Cree <ecree.xilinx@...il.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>> ---
>> drivers/net/ethernet/sfc/Kconfig | 1 +
>> drivers/net/ethernet/sfc/efx_cxl.c | 21 +++++++++++++++++++++
>> 2 files changed, 22 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig
>> index c5fb71e601e7..7a23d6d6d85f 100644
>> --- a/drivers/net/ethernet/sfc/Kconfig
>> +++ b/drivers/net/ethernet/sfc/Kconfig
>> @@ -68,6 +68,7 @@ config SFC_MCDI_LOGGING
>> config SFC_CXL
>> bool "Solarflare SFC9100-family CXL support"
>> depends on SFC && CXL_BUS >= SFC
>> + depends on CXL_REGION
>> default SFC
>> help
>> This enables SFC CXL support if the kernel is configuring CXL for
>> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
>> index 5a08a2306784..4395435af576 100644
>> --- a/drivers/net/ethernet/sfc/efx_cxl.c
>> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
>> @@ -24,6 +24,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>> struct pci_dev *pci_dev = efx->pci_dev;
>> DECLARE_BITMAP(expected, CXL_MAX_CAPS);
>> DECLARE_BITMAP(found, CXL_MAX_CAPS);
>> + resource_size_t max_size;
>> struct efx_cxl *cxl;
>> u16 dvsec;
>> int rc;
>> @@ -89,6 +90,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>> return rc;
>> }
>>
>> + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1,
>> + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2,
>> + &max_size);
>> +
>> + if (IS_ERR(cxl->cxlrd)) {
>> + pci_err(pci_dev, "cxl_get_hpa_freespace failed\n");
>> + rc = PTR_ERR(cxl->cxlrd);
>> + return rc;
> return PTR_ERR(cxl->cxlrd);
OK.
Thanks!
>> + }
>> +
>> + if (max_size < EFX_CTPIO_BUFFER_SIZE) {
>> + pci_err(pci_dev, "%s: not enough free HPA space %pap < %u\n",
>> + __func__, &max_size, EFX_CTPIO_BUFFER_SIZE);
>> + rc = -ENOSPC;
>> + cxl_put_root_decoder(cxl->cxlrd);
>> + return rc;
>> + }
>> +
>> probe_data->cxl = cxl;
>>
>> return 0;
>> @@ -96,6 +115,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>>
>> void efx_cxl_exit(struct efx_probe_data *probe_data)
>> {
>> + if (probe_data->cxl)
>> + cxl_put_root_decoder(probe_data->cxl->cxlrd);
>> }
>>
>> MODULE_IMPORT_NS("CXL");
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