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Message-ID: <20250409122830.1977644-15-karol.kolacinski@intel.com>
Date: Wed, 9 Apr 2025 14:25:00 +0200
From: Karol Kolacinski <karol.kolacinski@...el.com>
To: intel-wired-lan@...ts.osuosl.org
Cc: netdev@...r.kernel.org,
anthony.l.nguyen@...el.com,
przemyslaw.kitszel@...el.com,
Karol Kolacinski <karol.kolacinski@...el.com>,
Michal Kubiak <michal.kubiak@...el.com>,
Milena Olech <milena.olech@...el.com>
Subject: [PATCH v2 iwl-next 03/10] ice: use designated initializers for TSPLL consts
Instead of multiple comments, use designated initializers for TSPLL
consts.
Adjust ice_tspll_params_e82x fields sizes.
Remove ice_tspll_params_e825 definitions as according to EDS (Electrical
Design Specification) doc, E825 devices support only 156.25 MHz TSPLL
frequency for both TCXO and TIME_REF clock source.
Reviewed-by: Michal Kubiak <michal.kubiak@...el.com>
Reviewed-by: Milena Olech <milena.olech@...el.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
---
drivers/net/ethernet/intel/ice/ice_common.h | 19 +-
drivers/net/ethernet/intel/ice/ice_tspll.c | 203 ++++----------------
drivers/net/ethernet/intel/ice/ice_tspll.h | 29 +--
3 files changed, 64 insertions(+), 187 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index ce5f561fc481..83e991c160ba 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -74,11 +74,11 @@ union ice_cgu_r16 {
};
#define ICE_CGU_R19 0x4c
-union ice_cgu_r19 {
+union ice_cgu_r19_e82x {
struct {
u32 fbdiv_intgr : 8;
u32 fdpll_ulck_thr : 5;
- u32 misc15 : 3;
+ u32 misc15 : 1;
u32 ndivratio : 4;
u32 tspll_iref_ndivratio : 3;
u32 misc19 : 1;
@@ -89,6 +89,21 @@ union ice_cgu_r19 {
u32 val;
};
+union ice_cgu_r19_e825 {
+ struct {
+ u32 tspll_fbdiv_intgr : 10;
+ u32 fdpll_ulck_thr : 5;
+ u32 misc15 : 1;
+ u32 tspll_ndivratio : 4;
+ u32 tspll_iref_ndivratio : 3;
+ u32 misc19 : 1;
+ u32 japll_ndivratio : 4;
+ u32 japll_postdiv_pdivratio : 3;
+ u32 misc27 : 1;
+ };
+ u32 val;
+};
+
#define ICE_CGU_R22 0x58
union ice_cgu_r22 {
struct {
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index 2ec3a18f5dc3..d98bde911887 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -4,164 +4,42 @@
static const struct
ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
- /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
- {
- /* refclk_pre_div */
- 1,
- /* feedback_div */
- 197,
- /* frac_n_div */
- 2621440,
- /* post_pll_div */
- 6,
+ [ICE_TSPLL_FREQ_25_000] = {
+ .refclk_pre_div = 1,
+ .post_pll_div = 6,
+ .feedback_div = 197,
+ .frac_n_div = 2621440,
},
-
- /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-
- /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-
- /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
- },
-
- /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
- {
- /* refclk_pre_div */
- 5,
- /* feedback_div */
- 159,
- /* frac_n_div */
- 1572864,
- /* post_pll_div */
- 6,
- },
-
- /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
- {
- /* refclk_pre_div */
- 10,
- /* feedback_div */
- 223,
- /* frac_n_div */
- 524288,
- /* post_pll_div */
- 7,
- },
-};
-
-static const struct
-ice_tspll_params_e825c e825c_tspll_params[NUM_ICE_TSPLL_FREQ] = {
- /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
- {
- /* ck_refclkfreq */
- 0x19,
- /* ndivratio */
- 1,
- /* fbdiv_intgr */
- 320,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
+ [ICE_TSPLL_FREQ_122_880] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
},
-
- /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
- {
- /* ck_refclkfreq */
- 0x29,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 195,
- /* fbdiv_frac */
- 1342177280UL,
- /* ref1588_ck_div */
- 0,
+ [ICE_TSPLL_FREQ_125_000] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
},
-
- /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
- {
- /* ck_refclkfreq */
- 0x3E,
- /* ndivratio */
- 2,
- /* fbdiv_intgr */
- 128,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
+ [ICE_TSPLL_FREQ_153_600] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 6,
+ .feedback_div = 159,
+ .frac_n_div = 1572864
},
-
- /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
- {
- /* ck_refclkfreq */
- 0x33,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 156,
- /* fbdiv_frac */
- 1073741824UL,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
- {
- /* ck_refclkfreq */
- 0x1F,
- /* ndivratio */
- 5,
- /* fbdiv_intgr */
- 256,
- /* fbdiv_frac */
- 0,
- /* ref1588_ck_div */
- 0,
- },
-
- /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
- {
- /* ck_refclkfreq */
- 0x52,
- /* ndivratio */
- 3,
- /* fbdiv_intgr */
- 97,
- /* fbdiv_frac */
- 2818572288UL,
- /* ref1588_ck_div */
- 0,
+ [ICE_TSPLL_FREQ_156_250] = {
+ .refclk_pre_div = 5,
+ .post_pll_div = 6,
+ .feedback_div = 159,
+ .frac_n_div = 1572864
},
+ [ICE_TSPLL_FREQ_245_760] = {
+ .refclk_pre_div = 10,
+ .post_pll_div = 7,
+ .feedback_div = 223,
+ .frac_n_div = 524288
+ }
};
/**
@@ -227,7 +105,7 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_bwm_lf bwm_lf;
- union ice_cgu_r19 dw19;
+ union ice_cgu_r19_e82x dw19;
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
@@ -395,9 +273,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_lock_e825c ro_lock;
+ union ice_cgu_r19_e825 dw19;
union ice_cgu_r16 dw16;
union ice_cgu_r23 dw23;
- union ice_cgu_r19 dw19;
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
@@ -415,9 +293,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
- if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_156_250) {
- dev_warn(ice_hw_to_dev(hw),
- "TCXO only supports 156.25 MHz frequency\n");
+ if (clk_freq != ICE_TSPLL_FREQ_156_250) {
+ dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
return -EINVAL;
}
@@ -473,7 +350,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return err;
/* Choose the referenced frequency */
- dw16.ck_refclkfreq = e825c_tspll_params[clk_freq].ck_refclkfreq;
+ dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
if (err)
return err;
@@ -483,8 +360,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- dw19.fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
- dw19.ndivratio = e825c_tspll_params[clk_freq].ndivratio;
+ dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
+ dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
@@ -508,14 +385,14 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- dw23.ref1588_ck_div = e825c_tspll_params[clk_freq].ref1588_ck_div;
+ dw23.ref1588_ck_div = 0;
dw23.time_ref_sel = clk_src;
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
- dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
+ dw24.fbdiv_frac = 0;
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
if (err)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ethernet/intel/ice/ice_tspll.h
index 0e28e97e09be..609bbbc04d2b 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.h
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.h
@@ -4,38 +4,23 @@
/**
* struct ice_tspll_params_e82x
* @refclk_pre_div: Reference clock pre-divisor
+ * @post_pll_div: Post PLL divisor
* @feedback_div: Feedback divisor
* @frac_n_div: Fractional divisor
- * @post_pll_div: Post PLL divisor
*
* Clock Generation Unit parameters used to program the PLL based on the
* selected TIME_REF/TCXO frequency.
*/
struct ice_tspll_params_e82x {
- u32 refclk_pre_div;
- u32 feedback_div;
+ u8 refclk_pre_div;
+ u8 post_pll_div;
+ u8 feedback_div;
u32 frac_n_div;
- u32 post_pll_div;
};
-/**
- * struct ice_tspll_params_e825c
- * @ck_refclkfreq: ck_refclkfreq selection
- * @ndivratio: ndiv ratio that goes directly to the PLL
- * @fbdiv_intgr: TSPLL integer feedback divisor
- * @fbdiv_frac: TSPLL fractional feedback divisor
- * @ref1588_ck_div: clock divisor for tspll ref
- *
- * Clock Generation Unit parameters used to program the PLL based on the
- * selected TIME_REF/TCXO frequency.
- */
-struct ice_tspll_params_e825c {
- u32 ck_refclkfreq;
- u32 ndivratio;
- u32 fbdiv_intgr;
- u32 fbdiv_frac;
- u32 ref1588_ck_div;
-};
+#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
+#define ICE_TSPLL_NDIVRATIO_E825 5
+#define ICE_TSPLL_FBDIV_INTGR_E825 256
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
int ice_tspll_init(struct ice_hw *hw);
--
2.49.0
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